Grown nanofin transistors

Abstract

One aspect of the present subject matter relates to a method for forming a transistor. According to an embodiment of the method, a pillar of amorphous semiconductor material is formed on a crystalline substrate, and a solid phase epitaxy process is performed to crystallize the amorphous semiconductor material using the crystalline substrate to seed the crystalline growth. The pillar has a sublithographic thickness. A transistor body is formed in the crystallized semiconductor pillar between a first source / drain region and a second source / drain region. A surrounding gate insulator is formed around the semiconductor pillar, and a surrounding gate is formed around and separated from the semiconductor pillar by the surrounding gate insulator. Other aspects are provided herein.

Description

[0001] Cross References to Related Applications [0002] Priority is hereby claimed to the following applications: U.S. Application Serial No. 11 / 397,527, filed April 4, 2006, entitled "Nanowire Transistor With Surrounding Gate,"; U.S. Application No. 11 / 397,430, filed April 4, 2006, entitled "Grown Nanofin Transistors," and entitled "DRAM with Nanofin Transistors," filed April 4, 2006 ” (“DRAM With Nanofin Transistors,” U.S. Application No. 11 / 397,413; and the April 4, 2006 application, entitled “Tunneling Transistor With Sublithographic Channel,” ), which is incorporated herein by reference. technical field [0003] The present invention relates generally to semiconductor devices, and more particularly to nanofin transistors. Background technique [0004] There is a market driven need in the semiconductor industry to reduce the size of devices such as transistors and to increase the density of devices on a substrate. Some product goals include lower power consumption, ...

AI Technical Summary

Problems solved by technology

The surrounding gate structure provides desirable control over the transistor channel, but this structure is difficult to achieve in practice

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