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System, method and device for memory technology

A memory and storage controller technology, applied in the information field, can solve problems such as increased risk of memory errors

Active Publication Date: 2013-05-29
INTEL CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Risk of memory errors increases as transfer rate increases and voltage swing decreases

Method used

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  • System, method and device for memory technology
  • System, method and device for memory technology
  • System, method and device for memory technology

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Embodiment Construction

[0031] Embodiments of the invention are generally directed to systems, methods and apparatus for providing RAS (reliability, availability and serviceability) solutions within a certain set of volume constraints. In some embodiments, the computing system uses different cyclic redundancy code (CRC) schemes for write CRC overlays (or just write CRCs) and read CRC overlays (or just read CRCs). These CRC schemes can be provided while maintaining the same DRAM (Dynamic Random Access Memory) form factor currently used in the server and client market segments. For example, in some embodiments, CRC coverage is provided for reading and / or writing data without adding additional pins to the connector. As discussed further below, this can be accomplished by adding a user interval (UI) to the data frame and / or multiplexing CRC bits on existing pins.

[0032] figure 1 is a block diagram illustrating selected aspects of a write CRC scheme according to an embodiment of the invention. In the...

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Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for reliability, availability, and serviceability solutions for memory technology. In some embodiments, a host determines the configuration of the memory subsystem during initialization. The host selects a write cyclic redundancy code (CRC) mechanism and a read CRC mechanism based, at least in part, on the configuration of the memory subsystem. Other embodiments are described and claimed.

Description

technical field [0001] Embodiments of the present invention generally relate to the field of information technology, and more specifically, relate to systems, methods, and devices for solutions to reliability, availability, and serviceability of memory technologies. Background technique [0002] Memory subsystems are prone to errors for a number of reasons. If these errors are not handled properly, they can cause the computing system to malfunction. Redundant information in the form of error correcting codes (ECC) can be used to reduce errors such as transient (or soft) errors. As transfer rates increase and voltage swings decrease, the risk of memory errors increases. Contents of the invention [0003] The invention provides an integrated circuit, including: [0004] a first module for providing write cyclic redundancy code CRC coverage to data bits of a frame by appending M user intervals of CRC bits to N user intervals of data bits; and [0005] The second module pr...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F11/10
CPCG06F11/1004G06F11/08G06F11/10G06F12/00
Inventor K·贝恩斯J·H·萨蒙
Owner INTEL CORP