Control method and bus interface of RAM use right

A technology of bus interface and usage rights, which is applied to the control method of RAM usage rights and the field of bus interfaces, can solve the problems of unable to meet the requirements of communication speed and difficult to realize strict control of communication timing, so as to improve communication speed, increase speed, optimize The effect on overall performance

Active Publication Date: 2010-06-16
ZHEJIANG SUPCON TECH
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  • Abstract
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Problems solved by technology

[0005] The CPU calculates and processes the data according to the instruction sequence based on hardware resources. When the bus applies for the right to use RAM or data interaction between the bus and the RAM, the CPU responds to interrupts to complete the bus interface task. Due to the uncertainty of interruption time, it is difficult to achieve strict control of communication timing and cannot meet the requirements of communication speed

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  • Control method and bus interface of RAM use right
  • Control method and bus interface of RAM use right
  • Control method and bus interface of RAM use right

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Embodiment Construction

[0045] Hereinafter, the method for controlling the use of RAM and the implementation of the bus interface of the present invention will be described in detail through specific embodiments in conjunction with the drawings.

[0046] figure 1 It is a schematic diagram of the structure of the bus interface of the present invention, such as figure 1 As shown, the bus interface includes: a bus data processing module 110, a CPU interface module 120, an arbitration module 130, and a RAM interface module 140; among them,

[0047] The bus data processing module 110 is used to receive data from the bus, and when determining the use of RAM according to the received data, send an application for the right to use RAM to the arbitration module 130; also used to when the arbitration module 130 determines that the bus data processing module 110 obtains RAM When using the right, the RAM interface module 140 is used to access data with the RAM; it is also used to output the data read from the RAM to t...

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Abstract

The invention discloses a bus interface, which comprises a bus data processing module, a CPU interface module, an arbitration module, and an RAM interface module. The bus data processing module and the CPU interface module send an RAM use right application to the arbitration module, and the arbitration module confirms the users of the RAM. The invention simultaneously discloses an RAM use right control method, and the method and the bus interface can effectively control communication sequential, and increases communication speed, efficiency and real-time performance.

Description

Technical field [0001] The invention relates to the field of industrial control and communication, in particular to a method for controlling the use right of RAM and a bus interface. Background technique [0002] The bus interface is a junction point connecting one or more microprocessors (CPUs) on the one hand and the bus on the other hand. [0003] Currently, the communication between the CPU and the data bus generally uses a universal asynchronous receiver transmitter (UART) in the CPU as a bus interface. Most CPUs have one or two UARTs. As an important part of the CPU’s I / O interface, UARTs are mainly used to convert between serial data streams and parallel data streams, that is: the received The serial data on the bus is converted into parallel data and provided to the bus in the CPU, and the parallel data on the bus in the CPU is converted into serial data and transmitted to the bus. [0004] The bus and the random access memory (RAM) are connected through the CPU. When the b...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/16G06F13/42
Inventor 宓霄凌陆晔张晓刚
Owner ZHEJIANG SUPCON TECH
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