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Structure for testing reliability analysis of integrated circuit inner layer dielectric

A technology of integrated circuits and test structures, applied in circuits, electrical components, electric solid devices, etc., can solve problems such as easy burning of metal wires and abnormal testing, and achieve the effect of reducing the possibility

Active Publication Date: 2009-07-29
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] For the circuit structure currently used for reliability analysis, in actual use, the metal wire pattern in the test structure is too small, and the metal wire has a zigzag corner shape, which causes the metal wire to be easily burned in the actual test, making the The problem that test can not carry out normally, proposes the present invention

Method used

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  • Structure for testing reliability analysis of integrated circuit inner layer dielectric
  • Structure for testing reliability analysis of integrated circuit inner layer dielectric
  • Structure for testing reliability analysis of integrated circuit inner layer dielectric

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Embodiment Construction

[0024] In order to better understand the technical solutions provided by the present invention, the following will be further described in conjunction with specific examples of the present invention, but they do not limit the present invention.

[0025] One of the preferred embodiments of the present invention is described in detail below to illustrate the concept of the present invention and to show the more important inventive features of the present invention.

[0026] figure 2 It is a schematic structural diagram for testing the reliability analysis of the inner layer dielectric of the integrated circuit for a specific embodiment of the present invention, such as figure 2 As shown, the test structure 2 consists of:

[0027] The metal wire structures 201 and 201', as components of the reliability test structure, are equivalent to metal wires used to form circuits in integrated circuit devices. Therefore, the design specifications of the metal structures 201 and 201', th...

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Abstract

The invention provides a testing structure for conducting reliability analysis to an inner dielectric of an integrated circuit, wherein, a metal wire adopted in the testing structure is in a straight line rod shape. The metal wire can be a plurality of metal lines which are in the straight line rod shape and connected with a dilated gasket respectively. The structure can completely avoid the situation that the test can not be carried out normally due to the easiness of burning down of the corners of the metal line when the voltage increases during the testing procedure. The structure can significantly reduce the possibility that the metal wire is burned down firstly in testing, thus facilitating the smooth implementation of the test and guaranteeing the accuracy of the test.

Description

technical field [0001] The invention relates to a reliability (Reliability) analysis process in the semiconductor manufacturing industry, in particular to a boost test method, in particular to an improved circuit structure for the boost test of the inner layer dielectric. Background technique [0002] In the structure of integrated circuit devices, the inner layer dielectric (ILD, Inter Layer Dielectric) refers to the insulating layer between metals, generally made of SiO 2 It is composed of non-conductive materials, and its function is to isolate different circuit structures from each other. The properties of the inner layer dielectric are crucial to the performance of semiconductor devices, and it is usually required to have good breakdown resistance. [0003] The boost method (Vramp methodology) can be used to test the performance of the inner layer dielectric. The main method of this method is to apply a constant step-up voltage to both ends of the inner layer dielectri...

Claims

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Application Information

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IPC IPC(8): H01L23/544
CPCH01L2924/0002
Inventor 阮玮玮陆黎明龚斌
Owner SEMICON MFG INT (SHANGHAI) CORP
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