Test structure for dielectric breakdown reliability analysis in integrated circuit and test method thereof

Abstract

The invention discloses a test structure of dielectric breakdown reliability analysis in an integrated circuit. The test structure comprises a lower layer metal wire structure, an upper layer metal wire structure, a through hole structure and a dielectric medium, wherein the lower layer metal wire structure comprises a first metal wire structure and a second metal wire structure which are arranged at intervals. The invention further discloses a test method of the test structure. The test method comprises the steps of providing a substrate, and forming an actual structure to be tested on the substrate according to the test structure; and measuring the dielectric breakdown reliability between adjacent metal wires of the lower layer metal wire structure in the actual structure to be tested, the dielectric breakdown reliability between the upper layer metal wire structure and the upper layer metal wire structure in the actual structure to be tested, and the dielectric breakdown reliability between a through hole and the adjacent second metal wire structure in the actual structure to be tested. The test structure disclosed by the invention can accurately evaluate places which require to be evaluated in dielectric medium voltage resistance of an actual circuit, thereby ensuring the accuracy of interconnecting wire reliability analysis.

Description

technical field [0001] The invention relates to the reliability (Reliability) field in the semiconductor manufacturing industry, in particular to a test structure and a test method for dielectric breakdown reliability analysis in integrated circuits. Background technique [0002] Reliability issues in Very Large Scale Integration (VLSI) are affected by device and interconnect technologies. With the reduction of the critical dimension, the gate delay of the device is reduced, and the interconnection performance of the circuit is also reduced. This is because the reduction of the feature size will lead to a reduction in the cross-sectional area and line spacing of the interconnection lines, and the parasitic effects caused by resistance, capacitance, and inductance will seriously affect the performance of the circuit. Therefore, the reliability of interconnection has become an important factor restricting the reliability of the system. In order to reduce the resistance-capac...

AI Technical Summary

Problems solved by technology

However, in an actual integrated circuit, the first metal line structure 112 and the upper layer metal line 132 are connected through a via structure 141, Figure 5 It is a cross-sectional view of the interconnection structure in the actual circuit, in Figure 5 In the actual circuit, the place with the worst dielectric withstand voltage capability between the interconnection lines includes the F1 position and the F2 position, Figure 5 The distance between the via structure 141 at the F3 position and the underlying metal line structure 102 is relatively close, even smaller than the widths of F1 and F2, and the F3 position is easily broken down when a voltage is applied, so the existing test structure has been It cannot reflect the place where the dielectric withstand voltage capability of the interconnection lines is the worst in the actual circuit, and cannot fully test the places where the dielectric withstand voltage capability needs to be evaluated, so that the accuracy of the reliability analysis of the interconnection lines cannot be guaranteed.

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