Structure for testing reliability analysis of integrated circuit inner layer dielectric

A technology of integrated circuit and test structure, applied in the direction of circuits, electrical components, electric solid devices, etc., can solve the problems of easy burning of metal wires and abnormal testing, and achieve the effect of reducing the possibility

Active Publication Date: 2011-02-02
SEMICON MFG INT (SHANGHAI) CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] For the circuit structure currently used for reliability analysis, in actual use, the metal wire pattern in the test structure is too small, and the metal wire has a zigzag corner shape, which causes the metal wire to be easily burned in the actual test, making the The problem that test can not carry out normally, proposes the present invention

Method used

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  • Structure for testing reliability analysis of integrated circuit inner layer dielectric
  • Structure for testing reliability analysis of integrated circuit inner layer dielectric
  • Structure for testing reliability analysis of integrated circuit inner layer dielectric

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Embodiment Construction

[0024] In order to better understand the technical solutions provided by the present invention, the specific embodiments of the present invention are further described below, but they do not limit the present invention.

[0025] One of the preferred embodiments of the present invention is described in detail below to describe the concept of the present invention and show the more important inventive features of the present invention.

[0026] figure 2 It is a schematic diagram of a test structure for reliability analysis of the internal dielectric of an integrated circuit according to a specific embodiment of the present invention, such as figure 2 As shown, the test structure 2 includes:

[0027] The first metal line structure 201 and the second metal line structure 201' are components of the reliability test structure. The metal line structure is equivalent to a metal line used to form a circuit in an integrated circuit device. Therefore, the design specifications and formation p...

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Abstract

The invention provides a testing structure for conducting reliability analysis to an inner dielectric of an integrated circuit, wherein, a metal wire adopted in the testing structure is in a straight line rod shape. The metal wire can be a plurality of metal lines which are in the straight line rod shape and connected with a dilated gasket respectively. The structure can completely avoid the situation that the test can not be carried out normally due to the easiness of burning down of the corners of the metal line when the voltage increases during the testing procedure. The structure can significantly reduce the possibility that the metal wire is burned down firstly in testing, thus facilitating the smooth implementation of the test and guaranteeing the accuracy of the test.

Description

Technical field [0001] The invention relates to a reliability analysis process in the semiconductor manufacturing industry, in particular to a boost test method, in particular to a circuit structure improved for the boost test of an inner layer dielectric. Background technique [0002] In the structure of integrated circuit devices, Inter Layer Dielectric (ILD) refers to the insulating layer between metals, generally composed of SiO 2 It is composed of other non-conductive materials, and its function is to isolate different circuit structures from each other. The properties of the inner dielectric are critical to the performance of the semiconductor device, and it is usually required to have good breakdown resistance. [0003] Vramp methodology can be used to test the performance of the inner layer dielectric. The main method of this method is to apply a constant stepped voltage to both ends of the inner layer dielectric. When the voltage rises to a certain level, the inner layer d...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/544
CPCH01L2924/0002
Inventor 阮玮玮陆黎明龚斌
Owner SEMICON MFG INT (SHANGHAI) CORP
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