Adaptive read and write systems and methods for memory cells

Abstract

Adaptive memory read and write systems and methods are described herein that adapts to changes to threshold voltage distributions of memory cells as of result of, for example, the detrimental affects of repeated cycling operations of the memory cells. The novel systems may include at least multi-level memory cells, which may be multi-level flash memory cells, and a computation block operatively coupled to the multi-level memory cells. The computation block may be configured to compute optimal or near optimal mean and detection threshold values based, at least in part, on estimated mean and standard deviation values of level distributions of the multi-level memory cells. The optimal or near optimal mean and detection threshold values computed by the computation block may be subsequently used to facilitate writing and reading, respectively, of data to and from the multi-level memory cells.

Description

[0001] Cross References to Related Applications [0002] This application claims U.S. Patent Application No. 60 / 864,468, filed November 6, 2006, entitled "Adaptive Read and Write Systems and Method for Flash Memory," and filed in 2007 Priority to U.S. Patent Application No. 60 / 910,325, entitled "Parameter Estimation for NVMemory," filed April 5, 2009, the entire disclosures of which are hereby incorporated by reference in their entirety. for all purposes. technical field [0003] Embodiments of the present invention relate to the field of data storage devices, and more particularly to storing data to and retrieving data from memory cells. Background technique [0004] Memory cells, such as flash memory cells, can store data by trapping a granulized amount of charge in isolated regions, such as transistors. In such devices, extracting data from a memory cell can usually be accomplished by applying a read voltage to a transistor and then estimating a read current determined...

AI Technical Summary

Problems solved by technology

[0012] Unfortunately, memory cells such as the multilevel flash memory cells described above can suffer from retention loss after being subjected to read and / or write cycles

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