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Hardware architecture for SATD fast implementation

A hardware architecture, fast technology, applied in the field of information, can solve problems such as computing a large number of SATD operations

Inactive Publication Date: 2009-11-18
HARBIN INST OF TECH SHENZHEN GRADUATE SCHOOL
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  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0007] In order to solve the problem that calculating SATD in the motion estimation of large-scale video images requires a large number of calculations, the present invention proposes a new hardware parallel computing architecture, which adopts four-stage pipeline technology, and its structure is as follows figure 1 shown

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  • Hardware architecture for SATD fast implementation
  • Hardware architecture for SATD fast implementation
  • Hardware architecture for SATD fast implementation

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specific Embodiment approach 2

[0026] Specific embodiment two: this embodiment has further illustrated the specific implementation method of the Hadamard transformation described in step A2 on the basis of specific embodiment one:

[0027] Step B1: In order to design the Hadamard transform hardware parallel computing architecture, first expand the Hadamard transform formula as follows:

[0028] DiffT = HAH T = d 11 d 12 d 13 d 14 d 21 d 22 ...

specific Embodiment approach 3

[0067] Embodiment 3: On the basis of Embodiment 2, this embodiment further illustrates the hardware parallel processing architecture of using a 4-2 compressor to design the Hadamard transformation matrix in step B3.

[0068] Step C1: figure 2 Computational matrix element d is given by 11 , d 21 , d 31 , d 41 The zeroth hardware structure circuit model of image 3 Computational matrix element d is given by 11 , d 21 , d 31 , d 41 Other bit hardware structure circuit models.

[0069] Step C2: Figure 4 Computational matrix element d is given by 12 , d 22 , d 32 , d 42 The zeroth hardware structure circuit model of Figure 5 Computational matrix element d is given by 12 , d 22 , d 32 , d 42 Other bit hardware structure circuit models.

[0070] Step C3: Figure 6 Computational matrix element d is given by 13 , d 23 , d 33 , d 43 The zeroth hardware structure circuit model of Figure 7 Computational matrix element d is given by 13 , d 23 , d 33 , d 43 ...

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Abstract

The SATD calculation is a key part in a motion estimation algorithm in video coding technologies, such as H.264, AVS and the like. The Hadamard transform is the core of the SATD calculation. At present, the general practice of the Hadamard transform is completed by two one-dimensional transforms. The invention designs a parallel hardware architecture for directly realizing Hadamard two-dimensional transform, thereby fully utilizing various rules during the Hadamard two-dimensional transform process in the parallel architecture and realizing the sharing of intermediate result, circuit resources and the like. The parallel hardware architecture designed in the invention can realize 4x4 Hadamard transform within a clock cycle.

Description

technical field [0001] The invention relates to a transformation method used in fractional pixel search in motion estimation of video coding, and a hardware-realized architecture of the method; the method is mainly used for estimating the code rate of a residual matrix after motion compensation. It belongs to the field of information technology. Background technique [0002] In the H.264 and AVS video coding systems, when performing fractional pixel motion estimation, it is necessary to calculate the SATD (Sum of Absolute Hadamard Transformed Differences) value. SATD calculation is processed with a 4×4 pixel block as the basic unit. In the H.264 and AVS coding systems, in order to complete the block selection, frame selection and other mode selections, it is necessary to calculate the SATD value frequently; and the Hadamard calculation process in SATD includes a large number of addition and subtraction operations, which makes the calculation of the entire SATD very large. ...

Claims

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Application Information

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IPC IPC(8): H04N7/26H04N19/43H04N19/436H04N19/63
Inventor 王明江张爱平颜琥商迪
Owner HARBIN INST OF TECH SHENZHEN GRADUATE SCHOOL
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