Multiple phase pulse generator

Abstract

A multiple phase pulse generator comprises n stages, where each stage comprises a first sub-stage (34, 38, 39, 40) and a second sub-stage (36, 42, 44). The first sub-stage has a first memory element (34) and the second sub-stage has a second memory element (36). The first memory element (34) of each stage is arranged to be set by the preceding stage. The first sub-stage (34, 38, 39 40) is arrangedto supply a stage output pulse (OUT) while the first memory element (34) is set. The second memory element (36) is arranged to be set by the stage output pulse (OUT). The second sub-stage (36, 42, 44) is arranged to hold the first memory element (34) reset after the stage output pulse (OUT) while the second memory element (36) is set.

Description

technical field [0001] The invention relates to a multiphase pulse generator. This generator can be used in devices such as displays. Background technique [0002] figure 1 A typical active matrix display is shown. The display consists of a matrix 2 of picture elements (pixels) arranged in M ​​rows and N columns. Each row and column is connected to one electrode, wherein the column electrodes are connected to the N outputs of the data driver 4 , and the row electrodes are connected to the M outputs of the scan driver 6 . [0003] Pixels are addressed one row at a time. The scan driver includes generating figure 2 A series of clock pulses is shown for the M-phase clock generator. Each clock phase OUT i Controls the activation of row i. Usually the pulses are non-overlapping, so no two pulses are high at the same time. [0004] All pixels of a row can be addressed simultaneously, or they can be addressed in B blocks of b pixels, where bB=N. In the latter case, the d...

AI Technical Summary

Problems solved by technology

[0010] However, this type of shift register has two disadvantages when it is required to generate pulses for the scan driver: first, the pulses have coincident edges (i.e. when Q i Q when falling i+1 rising), and second, there is no easy way to reverse its scan direction

However, this register requires at least three clock signals, and since its outputs overlap, additional logic and / or signals are required to generate non-overlapping output pulses

This additional clock increases the complexity of the circuitry controlling the registers and, in the case of registers formed on the display substrate, increases the number of connections to the display

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