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Method of forming integrated circuit structure

A technology for integrated circuits and interlayer dielectric layers, applied in the field of formation of isolation structures, can solve problems such as stress changes and easy generation of holes, and achieve the effects of reducing adverse stress and reducing changes in doping concentration.

Active Publication Date: 2009-12-02
MOSAID TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

This makes the shallow trench insulated 8 2 more prone to holes
This causes STI 8 2 The stress induced in the gate length direction changes unfavorably

Method used

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  • Method of forming integrated circuit structure
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  • Method of forming integrated circuit structure

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Embodiment Construction

[0018] Embodiments of the present invention provide a novel method for forming STI regions and resulting structures. The intermediate process steps of the preferred embodiment of the present invention will be described below. Variations of the preferred embodiment will be discussed next. Between the several embodiments of the invention and the drawings, like reference numerals will be used to designate like elements.

[0019] Figure 2A and Figure 2B A cross-sectional view of a semiconductor chip 18 including a semiconductor substrate 20 is shown. In one embodiment, as Figure 2A As shown, semiconductor substrate 20 is formed from a bulk of semiconductor material, such as silicon. In another embodiment, such as Figure 2B As shown, the semiconductor chip 18 has a silicon-on-insulator (SOI) structure, the semiconductor substrate 20 is located on a buried oxide layer (BOX) 22, and the buried oxide layer 22 is located on another semiconductor layer 24 .

[0020] Figure...

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PUM

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Abstract

A method of forming an integrated circuit structure includes providing a semiconductor substrate; forming a first isolation region in the semiconductor substrate; after the step of forming the first isolation region, forming a metal-oxide-semiconductor (MOS) device at a surface of the semiconductor substrate, wherein the step of forming the MOS device comprises forming a source / drain region; and after the step of forming the MOS device, forming a second isolation region in the semiconductor substrate.

Description

technical field [0001] The present invention relates to integrated circuits, and more particularly to the formation of isolation structures used to separate integrated circuits. Background technique [0002] Integrated circuits are formed on the surface of semiconductor substrates, primarily silicon substrates. The semiconductor elements are isolated from each other by an isolation structure close to the surface of the substrate. The isolation structure includes field oxides and shallow trench isolation (STI). [0003] Field oxide regions are often formed using local oxidation of silicon (LOCOS). A typical process includes blanket forming a mask layer on the substrate, and then patterning the mask layer to expose a portion of the underlying silicon substrate. Next, thermal oxidation is performed in an oxygen-containing atmosphere to oxidize the exposed portion of the silicon substrate. Next, the mask layer is removed. [0004] As the size of integrated circuits shrinks,...

Claims

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Application Information

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IPC IPC(8): H01L21/762H01L21/8234H01L21/336
CPCH01L21/76283H01L21/823481H01L21/84
Inventor 冯家馨
Owner MOSAID TECH
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