Method of forming integrated circuit structure
A technology for integrated circuits and interlayer dielectric layers, applied in the field of formation of isolation structures, can solve problems such as stress changes and easy generation of holes, and achieve the effects of reducing adverse stress and reducing changes in doping concentration.
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[0018] Embodiments of the present invention provide a novel method for forming STI regions and resulting structures. The intermediate process steps of the preferred embodiment of the present invention will be described below. Variations of the preferred embodiment will be discussed next. Between the several embodiments of the invention and the drawings, like reference numerals will be used to designate like elements.
[0019] Figure 2A and Figure 2B A cross-sectional view of a semiconductor chip 18 including a semiconductor substrate 20 is shown. In one embodiment, as Figure 2A As shown, semiconductor substrate 20 is formed from a bulk of semiconductor material, such as silicon. In another embodiment, such as Figure 2B As shown, the semiconductor chip 18 has a silicon-on-insulator (SOI) structure, the semiconductor substrate 20 is located on a buried oxide layer (BOX) 22, and the buried oxide layer 22 is located on another semiconductor layer 24 .
[0020] Figure...
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