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Memory access control device

A memory access and memory controller technology, applied in memory systems, instruments, memory address/allocation/relocation, etc., can solve problems such as inability to use memory, and achieve the effect of shortening memory access delay

Inactive Publication Date: 2010-03-10
NEC CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

Therefore, when a memory manager is using the memory 50, other memory managers cannot use the memory 50 until its access ends.

Method used

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Examples

Experimental program
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Embodiment

[0065] figure 1 is a diagram showing the structure of the first embodiment of the present invention. This embodiment includes a memory access control device 10 and a memory 50 with a plurality of storage banks. The memory access control device 10 includes: memory managers A (11), B (12); C (13), D (14); arbiter (20); secondary arbiter (30); memory controller 40.

[0066] figure 2 is showing figure 1 A diagram of an example of the structure of the arbiter 20. refer to figure 2 , in this embodiment, the arbiter 20 includes a coordination unit 21 and an access division unit 22, wherein the coordination unit 21 selects a memory manager from a plurality of memory managers 11-14, and the access division unit 22 When the access request consists of multiple burst lengths, the access request is divided into short burst lengths.

[0067] image 3 is showing figure 1 A diagram of an example of the structure of the sub-arbiter 30. refer to image 3 , in this embodiment, the...

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Abstract

A memory access control apparatus that makes it possible to reduce memory access latency of access from a prescribed memory master is provided in a unified memory architecture or multiprocessor system. The memory access control apparatus includes an arbiter (20) and a sub-arbiter (30) receiving and arbitrating access requests from a plurality of memory masters (11) to (14); a memory controller (40); and a memory (50) having a plurality of banks. When a bank of the memory used by an access request allowed by the arbiter (2) and currently being executed and a bank of the memory to be accessed byan access request by the sub-arbiter (30) are different and the type of access request allowed by the arbiter (20) and currently being executed and the type of memory access to be performed by the sub-arbiter are identical, then it is decided that access efficiency will not decline, memory access by the arbiter (20) is suspended and memory access by the sub-arbiter (30) is allowed to squeeze.

Description

technical field [0001] related application [0002] This application claims priority based on Japanese Patent Application No. 2007-117318 filed on April 26, 2007, the entire contents of which are incorporated herein by reference. [0003] The present invention relates to the access control device of memory, relate in particular to very suitable for shortening the memory access latency (Memory access latency) of specific memory manager (Memory Master) in unified memory architecture (Unified Memory Architecture) or multiprocessor system means of memory access control. Background technique [0004] In a unified memory architecture or a multiprocessor system, multiple memory managers share a memory and use it time-divided. [0005] Figure 5 is a diagram showing an example of a typical structure of a memory access control device. refer to Figure 5 It can be seen that in the memory access control device 10', the arbiter 20' coordinates the access requests from the plurality o...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/00G06F12/06
CPCG06F13/161
Inventor 泷泽哲郎
Owner NEC CORP
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