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Flash chip detecting method based on boundary scan

A chip detection and boundary scan technology, which is applied in the direction of measuring electricity, measuring devices, measuring electrical variables, etc., which can solve the problems of general limitations of chip testing and lack of systematic testing.

Inactive Publication Date: 2011-08-24
NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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Problems solved by technology

[0005] For the Flash chip that does not support the JTAG standard boundary scan, it does not yet have the function of systematic testing, so it is greatly limited in the universality of chip testing

Method used

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  • Flash chip detecting method based on boundary scan
  • Flash chip detecting method based on boundary scan
  • Flash chip detecting method based on boundary scan

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Embodiment Construction

[0023] The working principle of the present invention is as follows:

[0024] Connect the JTAG test ports TDI, TMS, TCK, TDO of the CPLD chip with the parallel port of the upper PC, and write the control instructions and target code of the JTAG port from the parallel port of the PC into the BSR (Boundary Scan Register) of the JTAG through the program , BSR is composed of BSC (Boundary Scan Cell) in series. When designing the PCB, connect the data scan chain, address scan chain, and control scan chain of the CPLD to the data line, address line, and control line of the tested Flash chip, respectively, because the CPLD data scan chain, address scan chain, and control scan chain Corresponding signals are sent to the BSC on the pins, and the signals can be sent to the tested Flash through the corresponding pins of the BSC.

[0025] In the present invention, the CPLD chip adopts the CPLD device LFXP2_5E_XXQ208 of Lattic Company, combined figure 1 with image 3 As shown, the method flow ...

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Abstract

The invention discloses a flash chip detecting method based on boundary scan, belonging to the field of boundary scan of chips. The method comprises the steps of: firstly, respectively connecting pins of three kinds of signal lines comprising data lines, address lines and control lines of the Flash chip to be detected with pins of any one of scan chains of a CPLD chip; then connecting the parallel port of a principal personal computer (PC) with four JTAG pins of the CPLD chip; sending binary signals to the corresponding pins to be detected from the principal PC through TDI pins; and observingthe waveforms of the corresponding signals through an oscillograph to judge the correctness of the connection of the pins. In the invention, the JTAG detection of the CPLD chip is used for indirectlydetecting the Flash chip without JTAG interfaces; and the method of the invention has convenient operation, low hardware cost and low testing cost, can be used for testing multiple control circuits, and reduces the quantity of peripheral testing interfaces.

Description

Technical field [0001] The invention relates to a chip detection method, in particular to a flash chip detection method based on boundary scanning, and belongs to the field of chip boundary scanning. Background technique [0002] SoC (System On a Chip) design is becoming more and more complicated, which not only increases the chip area, but also reduces the testability of circuits and systems sharply. Testing takes an increasing proportion of time in SoC design. Conventional test methods Is facing increasingly serious testing difficulties. [0003] With the shortening of the design and testing cycle, it has become an inevitable trend to combine testing and design to complete DFT (Design for Test-ability). Boundary scan technology, as an important design for testability technology, can not only test the debugging function of the entire SoC or PCB, but also test whether the connection between the modules is faulty. In 1990, IEEE and JTAG (Joint Test Action Group) jointly formulated...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G01R31/3185
Inventor 高尚丰立东顾娜陈亮亮安逸
Owner NANJING UNIV OF AERONAUTICS & ASTRONAUTICS
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