Trench type power semiconductor manufacturing method

Abstract

The invention discloses a method for manufacturing a trench type power semiconductor. First, a plurality of gate trenches are formed in the epitaxial layer. Then, a gate oxide layer is formed to fully cover the exposed surface of the epitaxial layer, and a plurality of polysilicon gates are formed in the gate trenches. Next, implanting dopants of the first conductivity type into the epitaxial layer through the gate oxide layer, and driving in the dopants of the first conductivity type in an oxygen-free environment to form a body. Next, doping of the second conductivity type is implanted into the body through the gate oxide layer, and these dopants of the second conductivity type are driven in in an oxygen-free environment to form a plurality of source doped regions. Then, using the gate oxide layer as a shield, a self-aligned metal silicide is formed on the polysilicon gate. Next, a dielectric layer is deposited on the epitaxial layer, and a contact window is made in the dielectric layer to expose the source doped region. Finally, a heavily doped region of the first conductivity type is formed in the body through the contact window.

Description

technical field [0001] The invention relates to a method for manufacturing a trench-type power semiconductor, in particular to a method for manufacturing a trench-type power semiconductor with low grid resistance. Background technique [0002] In order to meet the needs of energy saving and reduce system power loss, higher energy conversion efficiency is required. These design specifications that keep pace with the times will become increasingly severe challenges for power converter designers. In response to this demand, new power components play an increasingly important role in high-efficiency converters. Among them, the power metal oxide half field effect transistor (Power MOSFET) has been widely used in various power converters. [0003] Figures 1A to 1E The fabrication process of a typical trench power MOSFET is shown. In the figure, an N-type power metal oxide half field effect transistor is taken as an example. Such as Figure 1A As shown, an N-type epitaxial lay...

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Problems solved by technology

However, since the thickness of the silicon oxide layer 140b on the surface of the polysilicon gate 152 is greater than the thickness of the silicon oxide layer 140a on the surface of the epitaxial layer 120, it is difficult to remove only the silicon oxide layer 140b on the surface of the polysilicon gate 152 by overall etching. Retain the silicon oxide layer 140a on the surface of the epitaxial layer 120

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