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Error judging circuit and shared memory system

A memory system, error judgment technology, applied in the field of error judgment circuit and shared memory system, can solve difficult data guarantee and other problems

Inactive Publication Date: 2010-06-16
FUJITSU LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0014] In a conventional multiprocessor system or a shared memory system, a part of the main memory is used to store information for maintaining cache coherency, information for data assurance, information for protecting memory, etc., so that there is One problem: Difficulty enforcing data guarantees while improving the utilization efficiency of the main memory area without increasing the cost of the system

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  • Error judging circuit and shared memory system
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  • Error judging circuit and shared memory system

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Embodiment Construction

[0032] According to the disclosed error judgment circuit and memory sharing system, a first EOR circuit tree, a second EOR circuit tree and error detection circuit components are used. The first EOR circuit tree is used when using (k,k-3) Reed-Solomon code (k is not more than 2 m natural number) of S m EC-D m In ED, when P(x) is a primitive polynomial of order m (m is a natural number not less than 8) in Galois field GF(2), Galois extended field GF(2 m ) is α and the root of P(x)=0 is α i (i=0,...,m-1), through the Galois extension field GF(2 m ), for m-bit block unit data, calculate C(x)=x from the polynomial remainder related to the polynomial expression I(x) of the original code as the object to be protected from errors 2 I(x)modP(x) to generate the check digit of the correction code. The second EOR circuit tree is used when the polynomial expression of the code that is the object to be detected and may be mixed with errors is expressed as Y(x), with respect to the cod...

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Abstract

An error judging circuit includes a first EOR circuit tree that generates a check bit of a correction code by polynomial remainder calculation with respect to a polynomial expression of an original code which is protected from an error with respect to data of m bit block unit by addition in a Galois extension field GF (2 m ) in S m EC-D m ED using Reed-Solomon code, a second EOR circuit tree for generating syndromes from S n =Y(+- n ) with respect to code C(x) in which the check bit is added to the original code when a polynomial representation of a code which is to be detected an error and has a possibility that an error is mixed is Y(x), and an error detection circuit unit that detect if there is a one block error, a two block error, or no error based on whether or not an equation of syndromes S 1 2 =S 0 S 2 is satisfied.

Description

technical field [0001] The invention relates to an error judging circuit and a shared memory system. Background technique [0002] As a method for maintaining cache coherency in a multiprocessor system or a shared memory system, there are SMP (Symmetric Multiprocessing) systems and ccNUMA (Cache Coherent Non-Uniform Memory Access) systems. [0003] In the ccNUMA system, a full directory system is generally used in which the main memory is divided for each block having a size, and information called a directory for maintaining cache coherency is stored in the main memory for each block . In many cases, the block size is equal to the cache line size of the cache memory. [0004] There are methods for ensuring that the area used to store the directory is different from the area of ​​the main memory. However, when a memory other than the main memory is provided to store the directory, although an area used as the main memory can be secured, the cost of the system increases. ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C29/42G06F11/10
CPCH03M13/1575G06F11/1028H03M13/1515G06F7/52G06F11/00G06F12/00G06F13/14
Inventor 鹈饲昌树
Owner FUJITSU LTD