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Circuit board and preparation process thereof

A preparation process and circuit board technology, which is applied in the direction of circuits, semiconductor/solid-state device manufacturing, electrical components, etc., can solve the problems of non-stick soldering, insufficient stress resistance, and inability to disperse uniformly, so as to reduce non-stick soldering and avoid cracked effect

Active Publication Date: 2012-01-25
ADVANCED SEMICON ENG INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

That is to say, the pressure and tension on the wire bonding pad area 24b cannot be evenly distributed on the circuit board 20, so that the bonding wire bump b and the wire bonding pad area 24b will not stick to each other.
[0007] However, in order to improve the non-stick phenomenon between the wire bonding bump b and the wire bonding pad 24b, the thicknesses of the original wire routing area 24a and the wire bonding pad area 24b are reduced so that the wire routing area 24a and the wire bonding pad area 24b When the thickness is thinned from the original 20 microns to 10 microns, the wire bonding area 24a will be cracked due to insufficient stress resistance

Method used

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  • Circuit board and preparation process thereof
  • Circuit board and preparation process thereof
  • Circuit board and preparation process thereof

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Embodiment Construction

[0058] In order to make the above and other objects, features and advantages of the present invention more comprehensible, the specific embodiments are described in detail with accompanying drawings as follows.

[0059] Figure 3A It is a schematic diagram of a circuit board according to an embodiment of the present invention. Please refer to Figure 3A , in this embodiment, the circuit board 100 a includes a dielectric layer 110 , a circuit layer 120 and an insulating layer 130 . The wiring layer 100 a is disposed on the dielectric layer 110 , and the wiring layer 120 has a pad area 122 and a wiring area 124 . The insulating layer 130 is disposed on the circuit layer 120 , and the insulating layer 130 covers the wiring area 124 , wherein the thickness D2 of the pad area 122 is smaller than the thickness D1 of the wiring area 124 . In particular, in this embodiment, the thickness D2 of the pad area 122 is less than half of the thickness D1 of the wire area 124, and the pad ...

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PUM

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Abstract

The invention discloses a circuit board, which comprises a dielectric layer, a circuit layer and an insulating layer, wherein the circuit layer is configured on the dielectric layer and is provided with a welding pad area and a wiring area; the insulating layer is configured on the circuit layer and covers the wiring area; and the welding pad area is thinner than the wiring area.

Description

technical field [0001] The present invention relates to a circuit board and its preparation process, and in particular to a circuit board with two different thickness regions in the same circuit layer and its preparation process. Background technique [0002] Wire bonding technology is a common chip packaging technology for electrically connecting the chip to a carrier, where the carrier is, for example, a circuit board. Generally speaking, the wire bonding technology is to use a wire bonding machine (stud bump machine) to form a wire bonding bump on the wire bonding pad area of ​​the carrier, and extend the wire bonding upward for a certain distance, and then turn to pull the wire to bond the chip. Pull the thread (stitch) away after the pad area. Through the wire bonding technology, the chip and the carrier can be electrically connected to each other through the bonding wire, and the signal can be transmitted between the chip and the carrier through the bonding wire. [...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L23/498H01L21/48
CPCH01L24/05H01L2224/04042H01L2224/48091H01L2224/48463
Inventor 李士璋陈昆进吕明龙李俊哲
Owner ADVANCED SEMICON ENG INC