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Semiconductor storage device

A storage device and semiconductor technology, applied in the direction of information storage, static memory, digital memory information, etc., can solve the problems of increased reading speed degradation, etc., and achieve the reduction of bit line load capacitance, large capacity, and large area reduction effect Effect

Inactive Publication Date: 2010-07-21
SOCIONEXT INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0006] Furthermore, with the miniaturization of the process, the speed degradation of multi-stage series transistors at low power supply voltages becomes more and more significant, and there is a problem that the reading speed degradation at low power supply voltages increases.

Method used

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  • Semiconductor storage device
  • Semiconductor storage device
  • Semiconductor storage device

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Experimental program
Comparison scheme
Effect test

Embodiment approach 1

[0029] figure 1 It is a circuit diagram of the semiconductor memory device according to Embodiment 1 of the present invention. figure 1 The semiconductor memory device includes a plurality of memory cells 100 that share a write bit line WBIT and a read bit line RBIT. Each memory cell 100 includes a memory circuit 10 that stores data, a write circuit 20 that writes data into the memory circuit 10 , and a read circuit 30 that reads data from the memory circuit 10 .

[0030] The memory circuit 10 has a PMOS transistor 11 and an NMOS transistor 12 constituting a first inverter, and a PMOS transistor 13 and an NMOS transistor 14 constituting a second inverter. The output node of the first inverter is connected to the input of the second inverter as the data holding node MD on the TRUE side, and the output node of the second inverter is connected to the input of the first inverter as the data holding node / MD on the BAR side .

[0031] The write circuit 20 has a PMOS transistor 2...

Embodiment approach 2

[0044] image 3 It is a circuit diagram of a semiconductor memory device according to Embodiment 2 of the present invention. image 3 The structural feature of the above is that the reset control signal RST is shared among multiple memory cells 100 connected to the same write word line WWL and the same read / write word line / RWWL. image 3 WBIT0 and RBIT0 in are the write bit line and read bit line for bit 0, respectively, and WBIT1 and RBIT1 are the write bit line and read bit line for bit 1, respectively. / PC0 and / PC1 are precharge control signals.

[0045] exist image 3 In the configuration described above, after the memory circuit 10 is initialized using the reset transistor 32 , writing of desired data is performed using the write circuit 20 . The advantage of this structure is that since the memory circuit 10 on the read / write word line / RWWL to be written is initialized by using the reset transistor 32 before writing, the write circuit 20 only needs to have the data ...

Embodiment approach 3

[0052] Figure 5 It is a circuit diagram of a semiconductor memory device according to Embodiment 3 of the present invention. exist Figure 5 Among them, 50 is a read and write circuit. The read / write circuit 50 not only has a switching transistor 31 connected to the TRUE side data holding node MD of the storage circuit 10 and the transistor control line DR for output wiring driving during reading and writing, but also includes a transistor control line DR for output wiring driving. The reset function also includes a reset transistor 32 for initializing the storage circuit 10, an output wiring driving transistor 33 connected to the read bit line RBIT, and a reset function for writing and initializing the storage circuit 10. The opposite data writing transistor 51 . / RWWL0 and / RWWL1 are the read and write word lines. In addition, DI is an input data signal, WE is a write enable signal, PLS is a pulse signal, 61 and 63 are AND gate circuits, and 62 is a NAND gate circuit. ...

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Abstract

A readout circuit (30) wherein a readout bit line (RBIT) is used as output wiring in a memory cell (100) is composed of a transistor (31) for switching, a transistor (32) for resetting and a transistor (33) for driving output wiring. The transistor (31) for switching connects a data holding node (MD) and a control line (DR) of a storage circuit (10) to each other by a control signal of the readout word line ( / RWL0). The transistor (32) for resetting resets a control line (DR) by a reset control signal (RST). The transistor (33) for driving output wiring is provided with a gate connected to the control line (DR), a drain connected to the readout bit line (RBIT), and a source connected to a ground power supply.

Description

technical field [0001] The present invention relates to a semiconductor storage device, in particular to a reading circuit of a storage unit. Background technique [0002] A semiconductor memory device having a multi-port structure is known. For example, a configuration is generally adopted in which a memory cell including a memory circuit, a write circuit, and two read circuits is used, and each read circuit is formed by connecting two or more stages of transistors in series between a bit line and a ground power supply. In this configuration, the gate of the transistor on the ground side is connected to the data holding node of the memory circuit, and the gate of the other transistor is connected to the word line (see Patent Document 1). [0003] Patent Document 1: Japanese Unexamined Patent Publication No. 5-12870 [0004] According to the conventional semiconductor memory device described above, in order to achieve the full amplitude of the bit line, a large-sized multi...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/41
CPCG11C11/419G11C8/16G11C11/412
Inventor 小池刚
Owner SOCIONEXT INC
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