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Dynamic pointer disambiguation

A pointer, dynamic technology, used in program control design, instrumentation, electrical digital data processing, etc.

Inactive Publication Date: 2010-08-11
NEMA LABS
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If it can be determined that two pointers will never access the same location, it may allow more program fragments to execute in parallel

Method used

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Examples

Experimental program
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Embodiment Construction

[0046] Dynamic pointer disambiguation techniques can produce faster dependency testing code than known techniques, and are useful for more complex code in high-level languages ​​such as C and C++ (other languages ​​are not excluded) (for example, using Structure - that is, struct-multidimensional pointers in the C programming language, and some control flow dependency issues) for analysis.

[0047] A method for generating dependency testing code to determine whether pointer accesses may overlap may include: (1) performing static analysis on a segment of code preceding code to be parallelized in order to (a) reduce the number of dependency tests that must be performed the amount of code, and (b) collect the information needed to test the code for dependencies; (2) use one of two published techniques to determine the memory intervals (i.e., the lowest and highest memory locations) that a pointer can access; and (3) Dependency test code is generated to ensure that memory interval...

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Abstract

Dynamic pointer analysis techniques are able to produce fasterpointer dependency test code and analyze more complex code in high-level languages such as in the programming languages C and C++ (not excluding other languages), as compared to known techniques.

Description

technical field [0001] This application relates to the field of multiprocessor computer systems and how to exploit multiple processors in such computer systems to accelerate programs designed for a single processor by exploiting thread-level parallelism. Background technique [0002] A multiprocessor computer includes multiple processors and memory. The memory includes a plurality of memory locations. A processor can use a read or write instruction to access a location in memory using the unique address of that location. The read and write instructions may be instructions commonly used in microprocessors. These instructions can also be implemented by a software program to emulate a global processor including locations accessible by multiple processors. [0003] Assuming N program segments, consider being divided into P 1 ,P 2 ,...,P N Enumerates a program of multiple program segments. The program segments must be executed one after the other in enumerated order for th...

Claims

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Application Information

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IPC IPC(8): G06F9/45
CPCG06F8/434
Inventor 亚历山大·布斯克米卡埃尔·恩布姆珀·施滕斯特伦弗雷德里克·沃格
Owner NEMA LABS
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