Impact-ionization metal oxide semiconductor transistor (I-MOS) and manufacturing method thereof

Abstract

The invention discloses an impact-ionization metal oxide semiconductor transistor (I-MOS) and a manufacturing method thereof. The method comprises the following steps: carrying out source electrode doping on a silicon substrate to obtain a source electrode; after depositing a silicon layer on the silicon substrate, carrying out light dope on the deposited silicon layer; photoetching a channel on the lightly doped silicon layer, and then manufacturing a grid electrode in the channel; carrying out oxidization on the surface of the silicon layer subjected to light dope and the top of the channelto obtain an oxidation layer, and then penetrating the oxidation layer to carry out drain electrode doping on the silicon layer subjected to light dope to obtain a drain electrode; and rapidly annealing to obtain the I-MOS. In the invention, the I-MOS manufacturing process is simple, the manufactured I-MOS has stable working performance, and the characteristic dimension can be reduced under the condition of not reducing the working performance.

Description

technical field [0001] The invention relates to the field of semiconductor device manufacturing, in particular to an impact ionization metal oxide semiconductor (I-MOS, Impact-Ionization MOS) transistor and a manufacturing method. Background technique [0002] An I-MOS transistor is a transistor with PIN diode characteristics in the gate region, which operates by adjusting the transistor channel length. The working performance of the I-MOS transistor is mainly reflected by two parameters: gate length (Lg, gate Length) and substrate length (Lin, intrinsic Length). Wherein, Lin represents the length of the substrate of the I-MOS transistor not covered by the gate. [0003] figure 1 It is a cross-sectional view of an I-MOS transistor in the prior art, as shown in the figure, the transistor includes a source, a drain and a gate, and there is a region between the source and the gate on the silicon substrate, which is to make the gate The polar region has the location of a PIN ...

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Problems solved by technology

[0014] Since the working performance of I-MOS transistors is determined by Lg and Lin, for example, the breakdown voltage is controlled by Lg and Lin, so there are problems in manufacturing I-MOS transistors in this way. Doping multiple times requires isolation from each other during doping. This manufacturing process is more complicated; secondly, the feature size (CD) of the manufactured I-MOS transistor cannot be reduced, because if the CD is reduced, its Lg and Lin will also be reduced accordingly, and the corresponding breakdown voltage will also decrease accordingly, reducing the performance of the I-MOS transistor; finally, the Lin of the PIN diode region between the gate and the source is difficult to control, because , when the source is heavily doped, due to the diffusion effect, the doped impurities on the silicon substrate will diffuse to the PIN diode region, resulting in the change of Lin in the PIN diode region, which will eventually lead to unstable performance of the manufactured I-MOS transistor , is not a pre-set operating performance

[0015] To sum up, the manufacturing of I-MOS transistors according to the prior art is complicated during manufacture, and the working performance of the manufactured I-MOS transistors is unstable, and the CD cannot be reduced without reducing the working performance.

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