On-line two-dimensional region management and task setting method of dynamically reconfigurable field programmable gate array (FPGA)

Abstract

The invention discloses an on-line two-dimensional region management and task setting method of a dynamically reconfigurable field programmable gate array (FPGA). The method comprises the following steps: searching unbounded hollow rectangles in a two-dimensional reconfigurable region; calculating the fragment degree of each unbounded hollow rectangular region according to the probability distribution of tasks and the unbounded hollow rectangles, and setting the tasks according to the fragment degrees, wherein the unbounded hollow rectangle searching process comprises: inputting an FPGA region matrix M and a newest deleted or inserted task, updating the region matrix M, finding out an updating interval of [L, R], namely the range of columns in which scan lines needing to be rescanned during adding or deleting hardware tasks are positioned; judging whether unscanned scan lines exist in the interval of [L, R]; and if an unscanned scan line i exists, utilizing an improved scan line algorithm to generate an unbounded hollow rectangle related to the scan line i, and returning to the step of judging whether the unscanned scan lines exist in the interval of [L, R] or not. By utilizing the method of the invention, the unbounded hollow rectangles can be efficiently searched, and the fragment degree of the region according to the probability distribution of the tasks, thereby conforming to actual systems better.

Description

technical field [0001] The invention relates to the technical field of reconfigurable computing research, in particular to a dynamic reconfigurable FPGA online 2D area management and task placement method. Background technique [0002] Field Programmable Gate Array (FPGA) is widely used in embedded system design because of its low power consumption, high performance and good flexibility of reconfigurable hardware devices. FPGA is composed of a certain number of CLB (Configurable Logic Block, reconfigurable logic block, referred to as cell) and the internal connections between them. FPGA is inherently parallel, that is, two or more hardware tasks can be executed on one FPGA simultaneously. Partially dynamically reconfigurable FPGAs, such as Xilinx's Virtex family, allow configuration of part of the FPGA region while the rest continue execution without interruption. That is to say, hardware tasks can be inserted and deleted dynamically. The FPGA can be 1D (one-dimensional) ...

AI Technical Summary

Problems solved by technology

However, since hardware tasks occupy areas of different sizes, while software tasks generally only occupy one CPU, in real-time task scheduling problems, it brings some new challenging problems, such as reconfigurable area management and task placement strategy, etc.

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