Junction formation on wafer substrates using group IV nanoparticles

A nanoparticle and wafer technology, applied in the field of nanoparticles, can solve the problems of limited manufacturing throughput, lack of simultaneous patterning, and constraints

Inactive Publication Date: 2011-05-04
INNOVALIGHT
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, these methods suffer from the lack of the ability to simultaneously pattern p-type and n-type doping
Furthermore, this method is inconsistent with the requirements of in-line processing and may have limited manufacturing throughput

Method used

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  • Junction formation on wafer substrates using group IV nanoparticles
  • Junction formation on wafer substrates using group IV nanoparticles
  • Junction formation on wafer substrates using group IV nanoparticles

Examples

Experimental program
Comparison scheme
Effect test

example 1

[0074]In this example, a 1 inch x 1 inch x 0.019 inch silicon wafer substrate doped with phosphorus to a resistivity of about 1 to 5 Ohmxcm was prepared by etching with NaOH, SC2, buffered oxide etch (BOE), and Piranha's Handle for cleaning.

[0075] Additionally, a p-type silicon nanoparticle ink was prepared from approximately 10.0 nm + / - 0.5 nm silicon nanoparticles in an inert environment as a solution in pyridine at 5 mg / ml using a 15% power sonicated horn Sonicate it for 15 minutes. A sufficient amount of silicon nanoparticle ink was applied to substantially cover the wafer surface and spin-coated at 1000 rpm for 60 seconds to form a silicon nanoparticle porous dense body. After baking the layer on a hot plate at 100°C for 30 minutes in an inert environment, it was spin-coated at 1000 rpm for 60 seconds to form a second silicon nanoparticle porous dense body, and then in an inert environment on Bake at 100°C for 30 minutes on a hot plate. The thickness of the formed s...

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Abstract

A method of forming a diffusion region is disclosed. The method includes depositing a nanoparticle ink on a surface of a wafer to form a non-densified thin film, the nanoparticle ink having set of nanoparticles, wherein at least some nanoparticles of the set of nanoparticles include dopant atoms therein. The method also includes heating the non-densified thin film to a first temperature and for afirst time period to remove a solvent from the deposited nanoparticle ink; and heating the non-densified thin film to a second temperature and for a second time period to form a densified thin film, wherein at least some of the dopant atoms diffuse into the wafer to form the diffusion region.

Description

technical field [0001] The present disclosure relates generally to nanoparticles, and in particular to Group IV nanoparticle junctions and devices formed therefrom. Background technique [0002] Semiconductors form the basis of modern electronics. Semiconductors are essential in most modern electronic devices (eg, computers, cellular telephones, photovoltaic cells, etc.) due to their physical properties that can be selectively changed and controlled between conducting and insulating. Group IV semiconductors generally refer to those elements in the fourth column of the periodic table (eg, carbon, silicon, germanium, etc.). [0003] In general, solid-state semiconductors tend to exist in three forms: lattice, polylattice, and amorphous. In lattice form, the semiconductor atoms are located in a single continuous unbroken lattice without grain boundaries. In the polylattice form, the semiconductor atoms are located in multiple smaller randomly oriented crystallites (smaller c...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L21/225H01L21/336H01L31/18H01L21/20H01L21/8238
CPCH01L21/02381H01L21/02488H01L21/02532H01L21/02573H01L21/02628H01L21/2256H01L21/2257H01L21/823892H01L29/66651H01L31/1804Y02E10/547Y02P70/50
Inventor 梅森·特里霍默·安东尼阿迪斯德米特里·波普拉夫斯基马克西姆·克尔曼
Owner INNOVALIGHT
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