Method and system for information interaction and resource distribution of multi-processor core

A multi-processor core and information interaction technology, applied in resource allocation, electrical digital data processing, instruments, etc., to achieve the effect of ensuring information exchange

Inactive Publication Date: 2014-01-08
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The technical problem to be solved by the present invention is to propose a solution and system for its information interaction and resource allocation for the multi-core SOC architecture

Method used

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  • Method and system for information interaction and resource distribution of multi-processor core
  • Method and system for information interaction and resource distribution of multi-processor core
  • Method and system for information interaction and resource distribution of multi-processor core

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Embodiment Construction

[0027] The core of the present invention is: configure the IPC array, each port of the IPC array is connected to a processor, and configure the group sending control register at the port, and control the information interaction between the processors through the operation of the group sending control register ; Inside the DMA controller, configure the channel application mask register and the interrupt orientation register connected to the interrupt controller of each processor, the channel application sent by the bus slave device is input into the channel application mask register of each DMA controller, and pass to all The selection operation of the channel application mask register is used to determine that the corresponding DMA controller responds to the corresponding channel application; the control logic module in the responding DMA controller sends an interrupt application, and through the selection of the interrupt orientation register, it is sent to the corresponding pr...

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Abstract

The invention discloses a method and a system for information interaction and resource distribution of a multi-processor core. The method comprises the following steps of: configuring an inter-process communication (IPC) array module in the system, wherein each port of the IPC array module is connected with a processor; configuring group sending control registers at the ports to control information interaction among the processors; configuring channel application shielding registers and interrupt directional registers connected with interrupt controllers of the processors in direct memory access (DMA) controllers, inputting channel applications to the channel application shielding registers of the DMA controllers, and determining response of the corresponding DMA controllers to the corresponding channel applications by selecting operation of the channel application shielding registers; and responding to interrupt applications sent by control logic modules in the DMA controllers, and sending the interrupt applications selected by the interrupt directional registers to the interrupt controllers of the corresponding processors. The method and the system can realize coordinated use and interrupt of the system on chip (SOC) resources in multiple central processing units (CPU) and ordered and effective distribution of the DMA resources among the multiple processors.

Description

technical field [0001] The present invention relates to the chip structure of large-scale (System on Chip system-on-chip) integrated circuit, be specifically related to a kind of complicated by multi-DSP processor (Digital Signal Processing digital signal processing) processor and multi-CPU (such as ARM processor) A method and system for information interaction and resource allocation under the SOC architecture. Background technique [0002] Integrated circuit SOC is widely used in communication, aviation, control and other fields. The integration level of modern SOC is getting higher and higher. For example, multi-core SOC including MCU (MicroControl Unit Chinese name is micro control unit) and DSP processor used in mobile phone baseband and application chips. The coexistence of multiple modes of mobile phones is a development trend, such as supporting GSM (Global System for Mobile Communications Global System for Mobile Communications), W-CDMA controller (Wide band Code ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F9/50G06F13/28
Inventor 陶建平王吉文方应龙汪坚
Owner SANECHIPS TECH CO LTD
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