Method for releasing card power up status bit of SD (secure digital) memory card and hardware circuit
A hardware circuit and electrical state technology, applied in static memory, information storage, instruments, etc., can solve the problems of not fast enough software execution, not too high, etc., and achieve the effect of reducing dependence and enhancing compatibility
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[0014] The structural block diagram of an embodiment of the hardware circuit adopted in the method of the present invention is as shown in the figure, including:
[0015] The command receiving circuit is responsible for receiving commands issued from the SD host.
[0016] The second synchronization circuit is connected with the command receiving circuit and is responsible for synchronizing the signal of the external SD clock domain to the internal clock domain.
[0017] The latch control circuit is connected with the second synchronous circuit and the latch register, receives the card power-on status bit OCR[31] signal of the OCR register, and transmits the card power-on status bit OCR[31] signal to the latch register.
[0018] The latch register is connected with the latch control circuit and the first synchronization circuit, and is used for latching the card power-on status bit OCR[31].
[0019] The first synchronization circuit is connected with the latch register and the...
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