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Novel two-transistor sonos flash memory cell structure and method of operation

A two-transistor, flash memory storage technology, applied in the field of new two-transistor SONOS flash memory cell structure

Active Publication Date: 2017-09-29
SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, the erasing of the SONOS storage unit of a single transistor is to use the substrate to erase the entire chip, or to erase the sub-blocks of the memory. The SONOS storage unit of the single transistor has the disadvantage of over-erasing, which requires peripheral circuits to perform erasure. complex erasure verification

Method used

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  • Novel two-transistor sonos flash memory cell structure and method of operation
  • Novel two-transistor sonos flash memory cell structure and method of operation
  • Novel two-transistor sonos flash memory cell structure and method of operation

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Embodiment Construction

[0022] The present invention will be described in further detail below in conjunction with accompanying drawing:

[0023] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, the present invention can be implemented in many other ways different from those described here, and those skilled in the art can make similar extensions without violating the connotation of the present invention, so the present invention is not limited by the specific implementations disclosed below.

[0024] Secondly, the present invention is described in detail using schematic diagrams. When describing the embodiments of the present invention in detail, for the convenience of explanation, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic diagram is only an example, and it should not be limited here. The protection scope of ...

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Abstract

The invention relates to a new dual-transistor SONOS flash memory storage unit structure and an operating method thereof. The dual-transistor SONOS flash memory storage unit structure includes a SONOS storage transistor and a storage unit selection tube. The selection gate of the storage unit selection tube As the selection end, the drain region on the side close to the gate of the memory cell selection transistor is the bit line end, the source region on the side close to the SONOS storage transistor is the source line end, and the control gate of the SONOS storage transistor is the control end. The operation method of the dual-transistor SONOS memory cell is to select the unit by the bit line terminal and the selection terminal during the read and write operations, and select the unit by the control terminal during the erase operation. The invention is fully compatible with standard CMOS logic technology and overcomes the over-erasure weakness of a single flash transistor storage unit.

Description

technical field [0001] The invention relates to an integrated circuit, in particular to a novel dual-transistor SONOS flash storage unit structure and an operation method thereof. Background technique [0002] Flash memory is a type of non-volatile memory that can be electrically erased and reprogrammed. Flash memory is erased and edited in blocks, where each block includes multiple memory cells. Each memory cell includes a floating-gate metal-oxide-semiconductor transistor for storing information. Each floating-gate MOS transistor stores one or more bits of data. One type of flash memory is polysilicon floating gate flash memory. Polysilicon floating gate flash memory is used for tunnel injection for writing data into memory cells and tunnel release for erasing data from memory cells. Flash memory is accessed as a block device. [0003] Another type of non-volatile memory is charge trapping memory, specifically Semiconductor-Oxide-Nitride-Semiconductor (SONOS) floating...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/1157G11C16/04H10B43/35H10B69/00
Inventor 张博
Owner SHANGHAI HUAHONG GRACE SEMICON MFG CORP
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