Signal event upset resistance D trigger capable of being set

An anti-single-event, trigger technology, applied in the direction of electrical pulse generator circuits, pulse generation, electrical components, etc., can solve the problem of low anti-single-event flipping ability, and achieve the effect of improving the anti-single-event flipping ability.
CN102394596AActive Publication Date: 2012-03-28NAT UNIV OF DEFENSE TECH
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Patent Information

Authority / Receiving Office
CN Β· China
Patent Type
Applications(China)
Current Assignee / Owner
NAT UNIV OF DEFENSE TECH
Publication Date
2012-03-28

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Abstract

The invention discloses a signal event upset resistance D trigger capable of being set and is aimed at raising signal event upset resistance capability of the signal event upset resistance D trigger capable of being set. The trigger comprises a clock circuit, a main latch register, a secondary latch register, and an output buffer circuit. The main latch register is composed of 12 PMOS tubes and 12 NMOS tubes. The secondary latch register is composed of 12 PMOS tubes and 12 NMOS tubes. Both the main latch register and the secondary latch register are subjected to duplication redundancy reinforcement, and C2MOS circuits in the main latch register and the secondary latch register are improved, i.e., a pull-up PMOS tube and a pull-down tube which are mutually redundant in the C2MOS circuit are separated. The trigger in the invention has strong signal event upset resistance capability, is suitable for a standard cell of a signal event upset resistance reinforcement integrated circuit, and is applied to the fields of aviation, spaceflight and the like.
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Description

technical field

[0001] The invention relates to a master-slave D flip-flop with a setting structure, in particular to a settable D flip-flop resistant to single event upset (signal event upset). Background technique

[0002] In cosmic space, there are a large number of high-energy particles (protons, electrons, heavy ions) and charged particles. After the integrated circuit is bombarded by these high-energy particles and charged particles, an electronic pulse will be generated in the integrated circuit, which may cause the original level of the internal node of the integrated circuit to flip. This effect is called single event upset (SEU). The higher the LET (Linear Energy Transfer) value of a single event bombarding an IC, the stronger the resulting electron pulse. Integrated circuits used in aviation and aerospace fields are threatened by single event upsets, which can make integrated circuits work unstable and even cause fatal errors. Therefore, it is particularly import...

Claims

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