Single event upset resistant settable scanning structure D trigger
An anti-single-event, trigger technology, applied in the direction of electrical pulse generator circuits, pulse generation, electrical components, etc., can solve the problem of low anti-single-event flipping ability.
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[0031] figure 1 It is a schematic diagram of the logic structure of the anti-single-event flip-flop D flip-flop of the scanning structure that can be set in the present invention. The present invention consists of a clock circuit (such as figure 2 shown), scan control buffer circuit (such as image 3 shown), the master latch (as Figure 4 shown), slave latches (as Figure 5 shown), the output buffer circuit (such as Image 6 shown) composition. The present invention has five inputs and two outputs. The five input terminals are respectively CK is the clock signal input terminal, D is the data signal input terminal, SE is the scanning control signal input terminal, SI is the scanning data input terminal and SN is the set signal input terminal; the two output terminals are Q and QN, Q and QN output a pair of opposite data signals. The clock circuit receives CK, and outputs C and CN respectively after buffering CK. The main latch receives D, C, CN, SE, SEN, SI, and SN, an...
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