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Signal event upset resistance D trigger capable of being set

An anti-single event and trigger technology, applied in the direction of electric pulse generator circuit, pulse generation, electrical components, etc., can solve the problem of low anti-single event flipping ability, and achieve the effect of improving the anti-single event flipping ability

Active Publication Date: 2013-12-11
NAT UNIV OF DEFENSE TECH
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0008] The technical problem to be solved by the present invention is to propose a settable D flip-flop that can resist single-event flip-flops, which can operate at a higher LET value. Works fine under single event bombardment without single event flipping

Method used

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  • Signal event upset resistance D trigger capable of being set
  • Signal event upset resistance D trigger capable of being set
  • Signal event upset resistance D trigger capable of being set

Examples

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Embodiment Construction

[0025] figure 1 It is a schematic diagram of the logic structure of the settable D flip-flop against single event upset of the present invention. The present invention consists of a clock circuit (such as figure 2 shown), the master latch (as image 3 shown), slave latches (as Figure 4 shown), the output buffer circuit (such as Figure 5 shown) composition. The present invention has three inputs and two outputs. The three input terminals are CK, which is the clock signal input terminal, D, which is the data signal input terminal, and SN, which is the set signal input terminal; the two output terminals are Q and QN, and Q and QN output a pair of opposite data signals. The clock circuit receives CK, and outputs C and CN respectively after buffering CK. The main latch receives D and C, CN and R, and the main latch outputs MO after latching D under the control of C, CN and R. The slave latch receives MO, C, CN and R, and the slave latch outputs SO after latching and other...

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Abstract

The invention discloses a signal event upset resistance D trigger capable of being set and is aimed at raising signal event upset resistance capability of the signal event upset resistance D trigger capable of being set. The trigger comprises a clock circuit, a main latch register, a secondary latch register, and an output buffer circuit. The main latch register is composed of 12 PMOS tubes and 12 NMOS tubes. The secondary latch register is composed of 12 PMOS tubes and 12 NMOS tubes. Both the main latch register and the secondary latch register are subjected to duplication redundancy reinforcement, and C2MOS circuits in the main latch register and the secondary latch register are improved, i.e., a pull-up PMOS tube and a pull-down tube which are mutually redundant in the C2MOS circuit are separated. The trigger in the invention has strong signal event upset resistance capability, is suitable for a standard cell of a signal event upset resistance reinforcement integrated circuit, and is applied to the fields of aviation, spaceflight and the like.

Description

technical field [0001] The invention relates to a master-slave D flip-flop with a setting structure, in particular to a settable D flip-flop resistant to single event upset (signal event upset). Background technique [0002] In the universe, there are a large number of high-energy particles (protons, electrons, heavy ions) and charged particles. After the integrated circuit is bombarded by these high-energy particles and charged particles, an electronic pulse will be generated in the integrated circuit, which may cause the original level of the internal node of the integrated circuit to flip. This effect is called single event upset (SEU). The higher the LET (Linear Energy Transfer) value of a single event bombarding an IC, the stronger the resulting electron pulse. Integrated circuits used in aviation and aerospace fields are threatened by single event upsets, which can make integrated circuits work unstable and even cause fatal errors. Therefore, it is particularly import...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H03K3/013H03K3/02
Inventor 梁斌李鹏池雅庆刘必慰刘真李振涛陈建军何益百杜延康
Owner NAT UNIV OF DEFENSE TECH
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