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Method and apparatus for system testing using multiple processors

A processor and main processor technology, applied in the direction of instruments, measuring electronics, measuring devices, etc., can solve problems such as not supporting interactive testing

Active Publication Date: 2012-05-02
WSOU INVESTMENTS LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0009] Unfortunately, these existing methods have many limitations
The first limitation is the data format, because the test player knows nothing about the system under test, so it can only perform the most basic operations
The second limitation is that interactive testing (local or remote) is not supported; rather any test results must be checked offline
Moreover, these existing methods are implementation dependent and generally proprietary

Method used

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  • Method and apparatus for system testing using multiple processors
  • Method and apparatus for system testing using multiple processors
  • Method and apparatus for system testing using multiple processors

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Embodiment Construction

[0035] Provides various system testing capabilities for performing system under test (SUT: system under test) testing.

[0036]In one embodiment, a Test Instruction Set Architecture (TISA) is provided. A TISA is provided for performing system tests. TISA combines computer science capabilities with system testing capabilities to provide improved system testing capabilities, including interactive testing capabilities, remote testing capabilities, and various other capabilities as described herein. TISAs are formed by adapting software-based instruction set architectures (ISAs) with system test capabilities. A software-based ISA can use any suitable software programming language (eg, C++, Java, etc., and various combinations thereof) and can be implemented using any suitable processor. The system test capability may use any suitable TAP, such as the IEEE 1149.1 (also known as JTAG) TAP or any other suitable TAP. In general, a TISA is formed by combining atomic operations of so...

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PUM

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Abstract

An apparatus is provided for performing testing of at least a portion of a system under test via a Test Access Port (TAP) configured to access the system under test. The apparatus includes a first processor for executing instructions adapted for controlling testing of at least a portion of the system under test via the TAP, and a second processor for supporting an interface to the TAP. The first processor is configured for detecting, during execution of the test instructions, TAP-related instructions associated with control of the TAP, and propagating the TAP-related instructions toward the second processor. The second processor is configured for receiving the TAP-related instructions detected by the first processor and processing the TAP-related instructions. The first processor is configured for performing at least one task contemporaneously with processing of the TAP-related instructions by the second processor. An associated method also is provided.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of US Provisional Application Serial No. 61 / 157,412, filed March 4, 2009, and entitled "Testing Instruction Set Architecture," which is hereby incorporated by reference in its entirety. [0003] This application is related to U.S. Patent Application Serial No. 12 / 495237, entitled "Method and Apparatus for System Testing Using Multiple Instruction Types," Attorney Docket No. ALU / 130137, and to U.S. Patent Application Serial No. 12 / 495336, U.S. patent application titled "Method and Apparatus for System Testing Using Scan Chain Decomposition", attorney case number ALU / 130137-3, which was filed concurrently with this application, and the two patent applications It is incorporated herein by reference in its entirety. technical field [0004] The present invention relates to the field of system testing, more particularly but not limited to generating and controlling instructions for system...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G01R31/3185
CPCG01R31/318558G01R31/3185
Inventor 苏雷什·戈雅尔米歇尔·波特兰布拉德福德·范特鲁尤伦
Owner WSOU INVESTMENTS LLC