Test structure for monitoring source and drain polycrystalline silicon etching

Abstract

The invention discloses a test structure for monitoring source and drain polycrystalline silicon etching, comprising a plurality of columns of gate polycrystalline silicon arranged on an active region in parallel as well as source and drain polycrystalline silicon covered on the active region and the gate polycrystalline silicon, wherein the source and drain polycrystalline silicon arranged at two sides of the gate polycrystalline silicon forms source and drain regions; the source and drain regions in an odd column and an even column are respectively connected by using source and drain regionconnecting lines and are respectively led out to form a test port; and the gate polycrystalline silicon in an odd column and an even column is respectively connected by using a polycrystalline silicon gate connecting line and is respectively led out to form a test port. By using the test structure provided by the invention, the electric leakage problem caused by the residue of polycrystalline silicon obtained after the source and drain polycrystalline silicon is etched can be effectively monitored at the accept test stage of a silicon wafer, the fracture problem of the polycrystalline siliconobtained after the source and drain polycrystalline silicon is subjected to planarization etching can be effectively monitored, and risks for causing following loss can be reduced.

Description

technical field [0001] The invention relates to a monitoring and testing structure of a semiconductor integrated circuit manufacturing process, in particular to a testing structure for monitoring source and drain polysilicon etching. Background technique [0002] In the existing process of forming source and drain regions with polysilicon, the active area on the silicon wafer is isolated by shallow trench isolation, and the device includes a plurality of polysilicon gates formed on the active area and arranged in parallel. And the polysilicon gate is also covered with source and drain polysilicon, and the source and drain polysilicon is formed by first growing a layer of polysilicon on the surface of the entire silicon wafer on which the polysilicon gate is formed, and then etching the source and drain polysilicon; The source and drain polysilicon are separated by each of the polysilicon gates and form the source and drain regions of the device on both sides of each of the p...

AI Technical Summary

Problems solved by technology

However, in the existing process of forming the source and drain regions with polysilicon, there is no effective method for monitoring the above-mentioned etching residues, and failures are often found in the product testing stage, and then the problem caused by the etching residues is found after failure analysis, resulting in risk of subsequent loss

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