Middleware system of heterogeneous multi-core reconfigurable hybrid system and task execution method thereof

Abstract

The invention discloses a middleware system of a heterogeneous multi-core reconfigurable hybrid system and a task execution method thereof. The middleware system is characterized by comprising an application program management layer, a task dividing and scheduling layer, a driving and input/output layer and a communication interface layer, wherein the application program management layer is used for supplying the operation environment and programming interface of an application program to a user; the task dividing and scheduling layer is in charge of scheduling in the process of dividing, mapping and operating tasks; and the driving and input/output layer is used for integrating the drives as well as input and output interfaces of a plurality of IP (Internet Protocol) cores; the application program management layer is used for providing an application program interface and an operation run time library for an application layer; the task dividing and scheduling layer used for dividing and scheduling task requests through a task dividing module, a mapping module and a scheduling module; the driving and input/output layer is integrated with a hardware drive and utilizes a hardware resource of an FPGA (Field Programmable Gate Array) platform; and the communication interface layer is in charge of transmitting data between reconfigurable hardware platforms. According to the system provided by the invention, the throughput rate of the platform and the performance of the system are improved by carrying out relative monitoring and automatic parallelization on the tasks in the operating process. The system can be used for supplying middleware supports comprising task dividing, scheduling and the like to a heterogeneous reconfigurable hybrid system, so that the execution efficiency is improved.

Description

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AI Technical Summary

Benefits of technology

This new technology allows multiple cores within one computer chip to work together more efficiently without being limited due to their physical location on that single core device. It also includes various features like virtual machines or containers called partitions which are used during program startup phases when different parts have been loaded into memory. These techniques help improve performance while reducing power consumption compared to previous designs.

Problems solved by technology

Technics Problem addressed in this patents relates to developing new types of computer architectures capable of being easily configured without sacrificing their performance capabilities when needed again due to changes made over time. Current methods involve static configurations where configurational resources cannot change frequently, making them challenged because they require frequent updates even if some parts were changed very rarely. Additionally, existing software solutions lack adaptive feature sets and allow limited reuse across multiple processor cores. Therefore, technical means aim to develop better ways to enable dynamic reconfiguration while maintaining high overall throughput and efficient use of available computational capacity.

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