Signal acquisition device of memory bus

Abstract

The invention provides a signal acquisition device of a memory bus, which comprises a detecting buffer unit and an acquisition unit, wherein the detecting buffer unit is suitable for acquiring signals of commands / an address bus and / or a data bus between a memory controller and memory chip and buffering and outputting the signals, and the acquisition unit is suitable or converting the buffered and output signals into data. By means of selection of input impedance of the detecting buffer unit, the signals of the memory bus are unaffected when signal acquisition is performed for the memory bus. The detecting buffer unit is a memory buffer or a DDRx register, and the acquisition unit is an FPGA (field programmable gate array), a high-speed oscilloscope or a logical analyzer. By the aid of the signal acquisition device, the problem of signal integrity when the FPGA performs signal acquisition for the memory bus is solved, so that a method for effectively acquiring memory signals can be carried out without interfering normal operation of an original memory system. Besides, the problem that caches of the high-speed oscilloscope and the logical analyzer can be only used for storing data at short time intervals is solved, so that the signals can be continuously acquired and outputted.

Description

technical field [0001] The invention relates to the fields of high-performance computing and signal acquisition, in particular to a signal acquisition device for a memory bus. Background technique [0002] Collecting memory bus signals is the basis for hardware to capture memory access information in real time. Acquisition of memory access information: it can help software designers improve memory access behavior and improve application software performance; it can help architecture designers find defects in existing memory systems, so as to improve them; it can also help hardware designers analyze memory protocols, Debug hardware. [0003] The memory bus includes a command bus, an address bus and a data bus, connecting the memory controller and memory particles, with a total width of about 100 bits. The existing memory bus acquisition methods are all bypass interception methods, where a certain place on the memory bus is selected as the acquisition point, and different de...

AI Technical Summary

Problems solved by technology

However, its shortcomings are also obvious: 1) The limited number of channels of the oscilloscope determines that it can only monitor certain bits in the 100-bit memory bus at the same time.

Although the logic analyzer can listen to signals with a width of hundreds of bits at the same time, it is difficult to find a position to fix its probe in a highly integrated motherboard in actual use, unless it is customized with its specific measurement interface (such as mid-bus) hardware

2) These two devices focus on collecting signals, but cannot effectively process the acquired information in real time, and their caches can only store data within a short time interval, and cannot continuously capture memory access information

3) High-speed oscilloscopes and logic analyzers are too expensive and not very versatile

The patent application with the application number US20060461567 discloses a system for monitoring the memory bus, but only some statistical information can be collected using counters

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