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Method and system for updating data after data reading of double-port RAM (random-access memory)

A technology for reading and updating data, which is applied in data conversion, electrical digital data processing, instruments, etc., and can solve problems such as no good solutions

Active Publication Date: 2012-07-25
SANECHIPS TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

At present, the existing technology does not have a good solution for this data update requirement

Method used

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  • Method and system for updating data after data reading of double-port RAM (random-access memory)
  • Method and system for updating data after data reading of double-port RAM (random-access memory)
  • Method and system for updating data after data reading of double-port RAM (random-access memory)

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Embodiment Construction

[0035] In the scheme of the present invention, the source end and the destination end work in different clock domains, that is, when the source end and the destination end transmit data across clock domains, the source end can write data into the dual-port RAM, and the destination end can read data from the dual-port RAM. Data, and after the destination end reads the data, the data can be written into the same dual-port RAM again after data processing, so as to meet the data update requirements of the dual-port RAM after reading the data.

[0036] A method for updating data after a dual-port RAM reads data, mainly comprising the following contents:

[0037] 1. Use the FIFO cache source as the data input cache source of the dual-port RAM. Under the action of the write enable signal that does not trigger the FIFO cache source, use the FIFO cache source to provide the write address signal and The write data signal prepares the buffer, and under the action of the write enable sign...

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Abstract

The invention discloses a method for updating data after data reading of a double-port RAM (random-access memory), which includes steps of preparing for caching write address signals and write data signals which are to be written into the double-port RAM by the aid of an FIFO (first-in first-out) cache source port before triggering write enable signals of the FIFO cache source port; preparing for caching read address signals and read data signals which are to be read out from the double-port RAM through an FIFO cache destination port before triggering the write enable signals of the FIFO cache destination port; and building chip select signals by null marking signals of the FIFO cache source port and null marking signals of the FIFO cache destination port, and writing data in the FIFO cache source port and the FIFO cache destination port into the double-port RAM in a time sharing manner. The invention further discloses a system for updating data after data reading of the double-port RAM. The method and the system for updating data after data reading of the double-port RAM can meet requirements for data updating after data reading process of the double-port RAM.

Description

technical field [0001] The invention relates to a technology for updating data of a dual-port random access memory (RAM), in particular to a method and a system for updating data after the dual-port RAM reads data. Background technique [0002] Dual-port RAM is a commonly used storage element in digital design. It can usually be used in any of the following three situations: (1) storing data; (2) transferring data by writing at the source and reading at the destination ; (3) Complete the clock domain conversion between the source end and the destination end. [0003] However, when the control function is completed in digital design, it is often a combination of the above three situations, that is: the source end and the destination end work in different clock domains, and the data is written into the dual-port RAM by the source end and read by the destination end. Use it after outputting the data. For the comprehensive application of the three cases, in order to reflect th...

Claims

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Application Information

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IPC IPC(8): G06F5/16
Inventor 徐心明刘伟达王红旗
Owner SANECHIPS TECH CO LTD