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Remote Core Operations in Multicore Computers

A multi-core processor and square core technology, applied in the computer field, can solve the problem of expensive cache coherence mechanism

Active Publication Date: 2015-12-02
MICROSOFT TECH LICENSING LLC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, cache coherency mechanisms are computationally expensive and use valuable interconnect resources

Method used

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  • Remote Core Operations in Multicore Computers
  • Remote Core Operations in Multicore Computers
  • Remote Core Operations in Multicore Computers

Examples

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Embodiment Construction

[0023] The detailed description provided below in connection with the accompanying drawings is intended as a description of examples of the invention and is not intended to represent the only forms in which examples of the invention may be constructed or used. This description sets forth the functionality of an example of the invention, and a sequence of steps for building and operating the example of the invention. However, the same or equivalent functions and sequences can be implemented by different examples.

[0024] Although examples of the invention are described and shown herein as being implemented in a multi-core computer system with shared physical memory and no cache coherency, the described systems are provided by way of example only, and not limitation. Those skilled in the art will appreciate that examples of the present invention are suitable for application in various different types of multi-core computer systems, including those with cache coherency.

[0025...

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Abstract

A multi-core processor with a shared physical memory is described. In an embodiment a sending core sends a memory write request to a destination core so that the request may be acted upon by the destination core as if it originated from the destination core. In an example, a data structure is configured in the shared physical memory and mapped to be accessible to the sending and destination cores. In an example, the shared data structure is used as a message channel between the sending and destination cores to carry data using the memory write request. In an embodiment a notification mechanism is enabled using the shared physical memory in order to notify the destination core of events by updating a notification data structure. In an example, the notification mechanism triggers a notification process at the destination core to inform a receiving process of a notification.

Description

technical field [0001] The computer technology of the present invention particularly relates to multi-core processors. Background technique [0002] Multi-core processors are increasingly widespread and are used to give performance gains in many application areas, where software processes are parallelized so that they run simultaneously on multiple cores. Each core may be considered a portion of a processor that performs the fetching and execution of instructions; for example, each core may be a central processing unit (CPU) within a single computing system. In general, a single-core processor can only process one sequence of instructions at a time. A multi-core processor has two or more independent cores that may be provided on a single physical device such as a chip or chip package. Multiple cores may or may not have access to shared physical memory, but this application is about multicore processors that do have shared physical memory. [0003] One or more shared physi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F15/167
CPCG06F15/167G06F12/0811G06F12/0815G06F12/1036G06F12/145G06F12/1483G06F2212/1041G06F2212/1056G06F2212/657G06F12/0802G06F12/084G06F12/0842G06F12/0866
Inventor R·J·布莱克T·哈里斯R·C·麦基尔洛伊K·斯特劳斯
Owner MICROSOFT TECH LICENSING LLC