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Ways to narrow the gap

A technology for reducing spacing and spacing, which is applied in the field of semiconductor technology, can solve problems such as insufficient size reduction, and achieve the effects of easy integration, low resolution, and high process tolerance

Active Publication Date: 2016-02-24
WINBOND ELECTRONICS CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] However, today's self-aligned double patterning can only reduce the size formed by the photolithography process to half, which is still not enough to overcome the trend of size reduction

Method used

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  • Ways to narrow the gap
  • Ways to narrow the gap
  • Ways to narrow the gap

Examples

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Embodiment Construction

[0017] In order to make the above and other objects, features and advantages of the present invention more comprehensible, preferred embodiments are listed below and described in detail in conjunction with the accompanying drawings.

[0018] The present invention will provide many different embodiments to implement different features of the present invention. The composition and configuration of each specific embodiment will be described below to simplify the present invention. These examples are not intended to limit the present invention. In addition, repeated element symbols may appear in various examples in this specification to simplify the description, but this does not mean that there is any specific relationship between the various embodiments and / or illustrations. In addition, "above", "on", "under" or "on" a first element formed on a second element may include that the first element is in direct contact with the second element in the embodiment, or may also include ...

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Abstract

One embodiment of the invention provides a method for narrowing pitch, which comprises: a step of providing a base material which comprises a first patterned material, wherein the pattern of the first material contains several wires with the same pitch, and the wires have a first width which is the same as the pitch between two adjacent wires; a step of forming a second material on the side wall of the wires, wherein the second material has a second width which is 1 / 3 of the first width; a step of removing the first material; a step of forming a third material on the side wall of the second material, wherein the third material has a third width which is 1 / 3 of the first width; a step of removing the second material; and a step of etching the base material so as to enable the base material to have many characteristics, wherein the pitch among the characteristics is 1 / 3 of the pitch between two adjacent wires.

Description

technical field [0001] The present invention relates to semiconductor processes, and more particularly to a method for reducing pitch in semiconductor processes. Background technique [0002] The photolithography process is an extremely important key procedure in the entire semiconductor process. How to reduce the critical dimension has always been a challenge for the photolithography process. For example, the element pitch of an integrated circuit, which is commonly used to measure the dimensions of repeated lines and spaces, is often limited by lithographic equipment and processes. When the half-pitch is less than 65 nm, especially less than 45 nm, the photolithography process will become extremely difficult. At present, there are many technologies that can achieve the purpose of size reduction. For example, self-alignment double patterning (selfalignment double patterning, SADP) is to achieve the purpose of size reduction by combining a photolithography process with oth...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L21/00H01L21/027G03F7/00
Inventor 刘丞祥蔡高财
Owner WINBOND ELECTRONICS CORP