89results about How to "Improve process tolerance" patented technology

Certain example embodiments relate to seals for glass articles. Certain example embodiments relate to a composition used for sealing an insulted glass unit. In certain example embodiments the composition includes vanadium oxide, barium oxide, zinc oxide, and at least one additional additive. For instance, another additive that is a different metal oxide or different metal chloride may be provided. In certain example embodiments, a composition may be combined with a binder solution that substantially or completely burns out by the time the composition is melted. In certain example embodiments, a CTE filler is included with a frit material. In certain example embodiments, a vacuum insulated glass unit includes first and second glass substrates that are sealed together with a seal that includes the above-described composition.

The invention provides a semiconductor high-voltage terminal structure and a production method thereof. The method comprises the steps of: firstly providing a silicon baseplate, forming a field oxide layer on the silicon baseplate and introducing an easily corroded layer in the field oxide layer; identifying a high-voltage terminal structure area by using a photomask; and then corroding the fieldoxide layer by using a wet method to form a ramp oxide layer with an oblique angle; carrying out ion implantation by using the ramp oxide layer as a self-aligned mask to introduce initial impurities diffusing horizontally; and finally forming a high-voltage protection ring with a horizontal doping gradient at the starting end of the ramp oxide layer; and forming a ramp field plate by depositing high-doping polycrystalline silicon or metal on the ramp oxide layer. The semiconductor high-voltage terminal structure comprises the silicon baseplate, the ramp oxide layer arranged on the silicon baseplate, the high-voltage protection ring with a horizontal doping gradient which is injected by taking the ramp oxide layer as the self-aligned mask, and the high-doping polycrystalline silicon or metal ramp field plate deposited on the ramp oxide layer.

The invention discloses a method for depositing a thin film. The method comprises the following steps of: providing a reaction chamber, wherein a substrate is placed on the surfaces of electrode plates which are alternately placed at intervals in the reaction chamber; leading reaction gas into the reaction chamber; exciting the reaction gas into plasmas by adopting a mode of pulse output radio frequency power; and depositing a thin film on the surface of the substrate. The method can obviously improve the band gap and the thickness uniformity of a thin film and particularly an alloy thin film deposited on the surface of the large-area substrate in large-size PECVD (Plasma Enhanced Chemical Vapor Deposition) deposition equipment.

A solid-state image pickup device comprises for each pixel a photoelectric converter PD, an input terminal FD of a signal amplifier and a transfer switch TX for transferring an optical signal from the photoelectric converter to the input terminal. The device additionally comprises means for resetting the photoelectric converter by opening the transfer switch TX under a condition of holding the voltage of the input terminal FD to a fixed high level before storing the optical signal in the photoelectric converter PD. With this arrangement, any residual electric charge in the photoelectric converter can be eliminated without paying the cost of reducing the manufacturing yield and degrading the chip performance.

The invention discloses a silicon-based InGaAs PIN photoelectric detector based on heterogeneous integration and vertical optical coupling. The silicon-based InGaAs PIN photoelectric detector comprises a silicon-on-insulator (SOI) substrate, a vertical coupling grating, a benzocyclobutene (BCB) bonding layer, an anti-reflecting layer, a first conductivity type indium phosphide layer, an intrinsic InGaAs layer and a second conductivity type indium phosphide layer, wherein the vertical coupling grating is produced in top silicon of the SOI substrate, the BCB bonding layer is covered on the vertical coupling grating, the anti-reflecting layer is located above the BCB bonding layer, the first conductivity type indium phosphide layer is located above the anti-reflecting layer, the intrinsic InGaAs layer is located above the first conductivity type indium phosphide layer, the second conductivity type indium phosphide layer is located above the intrinsic InGaAs layer, the vertical coupling grating is produced by etching the top silicon of the SOI substrate, the etching depth is 70-110 nm, the grating period is 600-680 nm, and the refractive index of the anti-reflecting layer is between refractive indexes of the BCB bonding layer and the first conductivity type indium phosphide layer. According to the silicon-based InGaAs PIN photoelectric detector, by means of an adhesiveness bonding process, InP/InGaAs/InP stack material layers are adhered to the grating which is etched on the SOI substrate, so that light and the InP/InGaAs/InP layers are vertically coupled, and suitable designs and prioritization schemes are provided for specific applications of the silicon-based InGaAs PIN photoelectric detector.

A touch panel and a peripheral circuit thereof are provided. Each bonding pad of the peripheral circuit includes a first conductive layer, a first protective layer, a second conductive layer, and a second protective layer sequentially arranged on a substrate from bottom to top. A covered area of the second conductive layer provided by the second protective layer is increased to cover a portion of the second conductive layer located above a junction area between the first protective layer and a terminal part of the first conductive layer, thereby increasing the reliability of the bonding pads.

Stabilized whole grain corn flour having extended storage stability and modified functional properties, such as improved processing tolerance, improved dough properties and enhanced corn flavors, is described, as are methods of making such stabilized whole grain corn flour.

The invention provides a silicon-based light transmitting-receiving component with parallel optical fiber transmission. The silicon-based light transmitting-receiving component with parallel optical fiber transmission comprises a silicon substrate, multiple electrodes, multiple lasers/detectors, multiple lenses, multiple optical fiber heads and an optical fiber cover plate, wherein the silicon substrate comprises a surface plane which is provided with recess parts, multiple wire slots and positioning parts; the positioning parts and the front ports of the wire slots are spaced by the recess parts; the electrodes are arranged in parallel and are arranged on the front section of the surface plane in a convex manner; the lasers/detectors are connected to the electrodes and are mounted on the surface plane through the positioning parts; the lenses are mounted in the recess parts to correspond to the lasers/detectors; the optical fiber heads are arranged in the wire slots; one ends of the optical fiber heads close to the lenses are covered with the optical fiber cover plate. Through the structure or the combination thereof, the silicon-based light transmitting-receiving component is realized, and accordingly the good effects of reducing the volume, bringing convenience to the manufacturing and lowering the cost are achieved.

A polarization beam splitter includes a silicon waveguide body of a thickness in rectangular shape with a width and a length between a first end plane and a second end plane. Two input ports are formed in the first end plane at two separate locations respectively next to two opposing length edges. The silicon waveguide body is configured to generate a plurality of direct or mirror images of an input optical signal provided through at least one of the two input ports. Two output ports are formed in the second end plane, one at a bar-position being configured to output a first output signal substantially in TE polarization mode and another at a cross-position being configured to output a second output signal substantially in TM polarization mode. Preferably, the width is 2.6 μm and the length is 40 μm with the thickness of a silicon layer of a SOI substrate.

The invention discloses a method for metal configuration with photoresist deposition. The method comprises: the surface of a substrate is coated with a photoresist; the substrate coated with the photoresist is baked, exposed, baked, and developed successively, wherein an included angle between the side wall of a photoresist graph after development and the surface of the substrate is between 80 degrees to 100 degrees; metal is deposited to the surface of the photoresist graph after development and the metal falls on the surface of the substrate at the opening of the photoresist; the metal on the surface of the substrate is removed; and the photoresist is removed. Therefore, a problem that the bottom width of the metal electrode or metal wire is much larger than the width of the top can be solved.

The invention discloses an infrared optical window with a three-step anti-reflection structure. The window comprises an infrared optical window body, the incident plane of the infrared optical windowbody is etched with the three-step anti-reflection structure, a preparation method comprises the steps that silicon wafer is pretreated, a metal pattern mask is used for etching the three-step anti-reflection structure on a silicon plate, the structure includes an etching first step structure layer, an etching second step structure layer and an etching third step structure layer, the method for etching the anti-reflection structure adopts an induction coupled plasma etching machine and a combination process of etching and passivation, the etching gas is SF6, the passivation gas is C4F8, and inert gas He is added during etching and passivation. The structure can obviously increase the transmittance of the infrared window, improve the sensitivity of infrared devices, and reduce influence ofthe height of a step structure, structural parameters and the variation of a step period and depth on the transmittance, and the preparation method improves process tolerance of device manufacturing,and reduces the difficulty of craft production.

The invention discloses a resistor and a production method of the resistor and a transistor with a metal gate. The production method includes: firstly, providing a substrate, and defining a transistor region and a resistor region on the substrate; secondly, forming the transistor with a dummy gate and the resistor in the transistor region and the resistor region respectively; thirdly, removing the dummy gate and part of the resistor so as to form a first trench and two second trenches in the transistor and the resistor respectively, and forming at least one high dielectric constant gate dielectric layer in each of the first trench and the second trenches; and finally, forming the metal gate and metal structures in the first trench and the second trenches respectively.

The invention discloses a manufacturing method for ohmic contact with low specific contact resistance and low roughness. The manufacturing method is characterized in that hardly compatible Mo metal is introduced to an ohmic contact metal seed to form a TiAlNiMoAu combination, thus the surface roughness and the specific contact resistance after alloying are reduced under the same alloying condition. In the manufacturing method, the low diffusivity of the Mo is utilized, and a binary alloy phase is matched, thus low contact resistance is realized, the roughness of the ohmic contact after alloying is also reduced, the overlay accuracy of a photolithographic process is improved, the number of process steps is reduced, the stability of the ohmic contact is improved, and a firm foundation is established for device process practicability.

The invention provides a silicon-based electro-absorption modulator and a preparation method thereof. The modulator uses voltage to adjust the light absorption coefficient of a semiconductor on the basis of an electro-absorption mode, and then the intensity of an optical signal is adjusted. Silicon is a weak electro-optical material, so that the silicon is introduced into material germanium whichhas a remarkable electro-optical absorption adjusting effect in a communication wave band C wave band and is compatible with the CMOS technology. Through an epitaxial growth modulation layer (200), light beams are smoothly coupled into and coupled out of the modulation layer (200), oscillation of light field power of the light beams between the modulation layer and a waveguide layer is not generated, the dependence relation between the insertion loss of a device and the length of the modulation layer is eliminated, meanwhile, different working wavelengths can be achieved by adjusting alloy components in the modulation layer (200), and the modulation efficiency is high.

The invention discloses a method for enhancing adhesion of a photoresist after developing. The method comprises the steps of 1, performing coating on the photoresist; 2, performing exposure and developing on the photoresist; 3, performing aligned measurement on the photoresist; 4, performing critical dimension measurement on the photoresist; 5, performing UVQ; 6, performing cleaning and wetting ona silicon wafer by deionized water; 7, performing high-dosage ion injection; 8, removing the photoresist; and 9, performing adhesive-removing examination on the photoresist. According to the method for enhancing adhesion of the photoresist after developing, cleaning and wetting of the silicon wafer by deionized water is added after the photoresist is completely developed, so that high adhesion between the photoresist and the silicon wafer can be ensured, the problem of photoresist peeling in high-dosage injection can be solved, and process margin is improved.

There is provided a thermosetting resin composition having excellent flowability, low temperature moldability, curability, and heat resistance after curing or the like in the absence of a solvent. The thermosetting resin composition of the present invention contains, as essential components, a maleimide compound (A), a compound (B) having two or more polymerizable unsaturated hydrocarbon groups in its molecule, and a cyanate ester compound (C).

The invention relates to the technical field of semiconductor manufacturing, in particular to a patterned sapphire substrate and a preparation method thereof. The patterned sapphire substrate comprises a sapphire flat sheet and a patterned silicon-containing organic coating formed on the surface thereof. A manufacture method comprises that follow steps of: (a) coating a silicon-containing organiccoating on the surface of a sapphire flat sheet; (b) coat a photoresist on that surface of the silicon-containing organic coating to form a photoresist layer, and photolithographically forming a maskpattern; (c) etching the silicon-containing organic coating under the protection of the photoresist layer, transferring the pattern to the silicon-containing organic coating, and removing the photoresist to obtain the patterned sapphire substrate. The invention replaces the traditional patterned sapphire substrate with a patterned silicon-containing organic coating, wherein the refractive index ofthe silicon-containing organic coating is lower than that of the sapphire, the scattering effect of the substrate on light can be effectively increased, and the luminous efficiency of the LED can beimproved; Moreover, its hardness is lower than that of sapphire, which increases the tolerance of photolithography and etching process and reduces the production cost.