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A Thyristor Electrostatic Discharge Protection Structure with Low Trigger Voltage

An electrostatic discharge protection, low trigger voltage technology, applied in circuits, electrical components, electrical solid devices, etc., can solve problems such as limiting ESD protection levels, and achieve high ESD protection levels, damage prevention, high current characteristics and protection capabilities. Effect

Active Publication Date: 2015-12-02
SHANGHAI BEILING
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] However, practical applications show that most of the failure sites of LVTSCR devices are on the NMOS tubes where avalanche breakdown occurs.
Although the NMOS tube reduces the trigger voltage of the entire LVTSCR protection structure, its ESD level limits the ESD protection level of the LVTSCR protection structure

Method used

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  • A Thyristor Electrostatic Discharge Protection Structure with Low Trigger Voltage
  • A Thyristor Electrostatic Discharge Protection Structure with Low Trigger Voltage
  • A Thyristor Electrostatic Discharge Protection Structure with Low Trigger Voltage

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Embodiment Construction

[0014] The present invention will be further described below in conjunction with accompanying drawing.

[0015] see Figure 4 , the thyristor electrostatic discharge protection structure with low trigger voltage of the present invention comprises a P-type substrate 1, on which P-type substrate 1 includes adjacent N well 2 and P well 3, and in N well 2 includes There are a first N-type implantation region 4 and a first P-type implantation region 5, and a second N-type implantation region 6, a third N-type implantation region 7 and a second P-type implantation region 8 are included in the P well 3. The surface between the second N-type implant region 6 and the third N-type implant region 7 includes a gate oxide layer 9, and the surface of the gate oxide layer 9 includes a polysilicon gate 10, wherein the first N-type implant region 4 and The first P-type injection region 5 is connected to the first input terminal I / OPAD; the third N-type injection region 7, the second P-type in...

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Abstract

The invention discloses a silicon controlled rectifier (SCR) electro-static discharge protection structure with low trigger voltage. The silicon controlled rectifier electro-static discharge protection structure comprises a P type substrate, the P type substrate comprises adjacent N trap and P trap, the N trap comprises a first N type injection region and a first P type injection region, the P trap comprises a second N type injection region, a third N type injection region and a second P type injection region, the surface between the second N type injection region and the third N type injection region comprises a gate oxide layer, and the surface of the gate oxide layer comprises a polycrystalline silicon grid. The first N type injection region and the first P type injection region are both connected with a first input end; the third N type injection region, the second P type injection region and the polycrystalline silicon grid are all connected with a second input end; and the second N type injection region is connected with the first input end by a resistor. With the adoption of the silicon controlled rectifier electro-static discharge protection structure, large current characteristics and protection capability of an SCR structure can be fully played, and a higher ESD (electro-static discharge) protection level is provided.

Description

technical field [0001] The invention relates to a structure of a semiconductor device, in particular to a low trigger voltage thyristor (SCR) electrostatic discharge protection structure. Background technique [0002] Electrostatic discharge (ESD) poses a great threat to the reliability of CMOS (ComplementaryMetalOxideSemiconductor, Complementary Metal Oxide Semiconductor) integrated circuits. In the widely used ESD protection circuit at present, the silicon controlled rectifier (SCR) structure has very good high current characteristics. Such as figure 1 As shown, it is a schematic diagram of a commonly used SCR structure. There are adjacent N wells and P wells on the P-type substrate, the P-type implanted region in the P-well, the N-type implanted region in the P-well, and the P-type The implanted region and the N-type implanted region in the N well form a PNPN semiconductor structure, I / OPAD is the first input terminal of the device, and GND is the second input terminal ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/02
Inventor 李飞鸣
Owner SHANGHAI BEILING