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Storage device connectting memory nodes having transmission function and data processing method

A storage device and data technology, which is applied in the direction of electronic digital data processing, input/output process of data processing, memory system, etc., can solve the problems of huge maintenance/management cost of route designation table, limited capacity expansion, complicated update procedures, etc.

Inactive Publication Date: 2012-10-03
TOSHIBA MEMORY CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0005] However, when a new memory node is added for capacity expansion, or when an existing memory node is deleted due to a failure or the like, it is necessary to update the path designation table of each memory node, and this update procedure is cumbersome.
In particular, when the number of storage nodes is large, the maintenance / management cost of the route designation table becomes huge, which limits the scalability of the capacity.
[0006] In addition, in a memory device in which memory nodes having a transfer function are connected to each other, when writing / reading a plurality of data to / from a plurality of memory nodes, it is generally difficult to simultaneously write and read a plurality of data through the same wiring. communication, it is easy to generate data transmission standby
This data transfer standby leads to an increase in the time required for data writing / reading

Method used

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  • Storage device connectting memory nodes having transmission function and data processing method
  • Storage device connectting memory nodes having transmission function and data processing method
  • Storage device connectting memory nodes having transmission function and data processing method

Examples

Experimental program
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no. 1 Embodiment approach

[0060] The first embodiment includes a storage device in which a plurality of memory nodes having a transfer function are mutually connected, and has a transfer method in which each memory node transfers a packet efficiently.

[0061] [1] Structure of storage device

[0062] figure 1 It is a diagram showing the configuration of the storage device according to the first embodiment, and shows an example of a method of physically arranging a plurality of memory nodes and an address allocation method for the physical arrangement.

[0063] As shown in the figure, the storage device 10 includes a plurality of memory nodes 11 having a data transfer function. Each memory node 11 is placed at grid points of a square grid. The logical address of the memory node located at grid coordinates (x, y) which is the grid point coordinates is set to (x, y) in agreement with the position coordinates. That is, the logical address of the memory node 11 matches the physical address (lattice coord...

no. 2 Embodiment approach

[0124] A storage device according to the second embodiment will be described. The second embodiment has a transfer algorithm 2 different from the transfer algorithm 1 included in the first embodiment. In the transfer algorithm 2, the transfer destination memory node is determined based on three pieces of information including the destination address, the source address, and the address of the own node included in the packet. In addition, the memory device has the same figure 1 as well as figure 2 Since they have the same structure, the description is omitted.

[0125] [1] Transfer algorithm 2 of storage device

[0126] Figure 10 It is a diagram showing the transfer algorithm 2 in the storage device according to the second embodiment. refer to Figure 10 , shows an example of a method of determining the adjacent node of the transfer destination based on three pieces of information: the destination address and the source address of the packet, and the address of the own ...

no. 3 Embodiment approach

[0146] A storage device according to the third embodiment will be described. The third embodiment has a different transfer algorithm 3 from the transfer algorithms 1 and 2 included in the first and second embodiments. In transfer algorithm 3, the transfer destination memory node is determined based on four pieces of information included in the packet, including the destination address and source address, the address of the own node, and the output port occupancy information of the own node. In addition, the memory device has the same figure 1 as well as figure 2 Since they have the same structure, the description is omitted.

[0147] [1] Transfer algorithm 3 of storage device

[0148] Figure 13 It is a diagram showing the transfer algorithm 3 in the storage device according to the third embodiment. refer to Figure 13 , shows an example of a method of determining the adjacent node of the transfer destination based on four pieces of information: the destination address an...

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PUM

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Abstract

According to one embodiment, a storage device includes a plurality of memory nodes. Each of memory nodes includes a plurality of input ports, a plurality of output ports, a selector, a packet controller and a memory. The selector outputs a packet input to the input port to one of the output ports. The packet controller controls the selector. The memory stores data. The memory nodes are mutually connected at the input ports and the output ports. The memory node has an address that is determined by its physical position. The packet controller switches the output port that outputs the packet based on information including at least a destination address of the packet and an address of the memory node having the packet controller when receiving a packet that is not addressed to the memory node having the packet controller.

Description

[0001] This application claims priority based on Japanese Patent No. 2010-252336 filed in Japan on November 10, 2010, the entire contents of which are hereby incorporated by reference. technical field [0002] Embodiments relate to a storage device and a data processing method in which memory nodes having a transfer function are mutually connected, and relate to, for example, a method of controlling transfer of data packets in the storage device. Background technique [0003] As a storage device that can easily expand capacity, a storage device in which memory nodes having a transfer function are mutually connected is considered. When receiving a packet addressed to its own memory node, each memory node performs predetermined processing such as reading or writing. On the other hand, when receiving a packet not addressed to its own memory node, each memory node transfers the received packet to an appropriate other memory node. By repeating appropriate transfer by each memory...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/16G06F3/06G06F13/10H04L45/74
CPCG06F3/0635G06F3/06G06F13/10H04L12/6418G06F13/16G06F13/1605H04L12/00G06F3/0601G06F3/0658G06F3/0656G06F3/0683G06F3/0605G06F13/14G06F12/00H04L2012/5603H04L45/74H04L49/253
Inventor 辰村光介木下敦宽西野弘刚铃木正道西义史丸亀孝生栗田贵宏
Owner TOSHIBA MEMORY CORP
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