Manufacturing method for NMOS (N-channel Mental-Oxide-Semiconductor) devices

Abstract

The invention relates to a manufacturing method for NMOS (N-channel Mental-Oxide-Semiconductor) devices. The manufacturing method comprises the following steps of: depositing silicon nitride layers with high tension stress on a provided substrate containing NMOSs; classifying the NMOSs uncovered by the silicon nitride layers before deposition in order according to the channel lengths of the NMOSs, reserving the silicon nitride layer to which the NMOS with the longest channel in the NMOSs corresponds, carrying out dry etching to remove the silicon nitride layers to which the rest of the NMOSs correspond, and depositing the silicon nitride layers again; repeatedly carrying out the steps till the NMOSs uncovered by the silicon nitride layers before deposition can not be classified in order according to the channel lengths of the NMOSs, and proceeding to carry out a follow-up universal semiconductor technology flow to form a NMOS transistor. The manufacturing method for the NMOS devices provided by the invention has the advantages of enabling the thickness of the silicon nitride layers to be in proportion to the channel length according to the channel lengths of the NMOSs through a deposition-dry etching removal-secondary deposition method and realizing the consistency of performance adjustment on the NMOS devices.

Description

technical field [0001] The invention relates to a semiconductor manufacturing process, and in particular to a manufacturing method of an NMOS device. Background technique [0002] With the development of semiconductor manufacturing technology, the characteristic line width of integrated circuit chips is getting smaller and smaller. In order to improve the performance of semiconductor devices, stress engineering technology is widely used in semiconductor technology to improve the electrical mobility of carriers. Among them, it is relatively common, for example, a contact etch stop layer (Contact Etch Stop Layer, CESL) stress engineering technology is used in the manufacturing process of the NMOS device. [0003] The stress engineering of the via etch stop layer is to generate high stress inside the film by adjusting the deposition conditions during the deposition of the via etch stop layer film, so that the stress is transmitted to the device channel, thereby affecting the ca...

AI Technical Summary

Problems solved by technology

[0005] At present, in actual production, in order to solve this problem, the influence of the channel length is usually considered in the layout design, so that the transistor design with a special structure is adopted, and the designed layout is continuously checked and corrected. Undoubtedly, the method greatly increases the R&D and production cycle and cost of the product

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