Memory system having memory and memory controller and operation method thereof

Abstract

An operation method of a memory system including a memory and a memory controller includes transmitting defective-cell address information to the memory controller from the memory at an initial operation of the memory, wherein the defective-cell address information includes an address of a defective cell of the memory, and accessing, by the memory controller, an area of the memory excluding an area indicated by the defective-cell address information inside the memory.

Description

[0001] Cross-references to related applications [0002] This application claims priority from Korean Patent Application No. 10-2011-0038528 filed Apr. 25, 2011, the entire contents of which are hereby incorporated by reference. technical field [0003] Exemplary embodiments of the present invention relate to a memory, a memory controller, and a memory system, and more particularly, to techniques for handling manufacturing defects in a memory. Background technique [0004] In the early days of the semiconductor memory industry, a large number of raw commodity dies (eg, blocks of semiconducting material) with defect-free cells fabricated in memory chips via semiconductor fabrication processes could be distributed over a semiconductor wafer. However, as memory capacity increases, it becomes difficult to manufacture memory chips with defect-free cells. Defective cells are repaired by a method in which spare memory, ie redundant memory, is provided in place of the defective cel...

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Therefore, these processes can increase the manufacturing cost of the memory

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