Strain SiGe vertical channel Si-based BiCMOS integrated device based on auto-alignment technology, and preparation method thereof
A self-aligned process, vertical channel technology, used in semiconductor/solid-state device manufacturing, electrical solid-state devices, semiconductor devices, etc., can solve the limitations of Si integrated circuit manufacturing process development, increase in integration and complexity, and have no replacement. Problems such as the conditions of the silicon-based process
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Embodiment 1
[0149] Embodiment 1: The preparation of a strained SiGe vertical channel Si-based BiCMOS integrated device and circuit based on a self-alignment process with a conductive channel of 45nm, the specific steps are as follows:
[0150] Step 1, preparation of the buried layer.
[0151] (1a) Select the doping concentration to be 5×10 14 cm -3 A P-type Si sheet as a substrate;
[0152] (1b) Thermally oxidize a layer of SiO with a thickness of 300nm on the substrate surface 2 layer;
[0153] (1c) Photoetching the buried layer region, implanting N-type impurities into the buried layer region, and annealing at 800° C. for 90 minutes to activate the impurities to form an N-type heavily doped buried layer region.
[0154] Step 2, deep trench isolation preparation.
[0155] (2a) Remove the redundant oxide layer on the surface, and epitaxially grow an N-type epitaxial Si layer with a thickness of 1.5 μm as the collector region, and the doping concentration of this layer is 1×10 16 cm ...
Embodiment 2
[0234] Embodiment 2: The preparation of the conductive channel is a strained SiGe vertical channel Si-based BiCMOS integrated device and circuit based on the self-alignment process, and the specific steps are as follows:
[0235] Step 1, preparation of the buried layer.
[0236] (1a) Select the doping concentration as 1×10 15 cm -3 A P-type Si sheet as a substrate;
[0237] (1b) Thermally oxidize a layer of SiO with a thickness of 400nm on the substrate surface 2 layer;
[0238] (1c) Photoetching the buried layer region, implanting N-type impurities into the buried layer region, and annealing at 900° C. for 60 minutes to activate the impurities to form an N-type heavily doped buried layer region.
[0239] Step 2, deep trench isolation preparation.
[0240] (2a) Remove the excess oxide layer on the surface, and epitaxially grow an N-type epitaxial Si layer with a thickness of 1.8 μm as the collector region, and the doping concentration of this layer is 5×10 16 cm -3 ;
...
Embodiment 3
[0319] Embodiment 3: The preparation of a strained SiGe vertical channel Si-based BiCMOS integrated device and circuit based on a self-alignment process with a conductive channel of 22nm, the specific steps are as follows:
[0320] Step 1, preparation of the buried layer.
[0321] (1a) Select the doping concentration to be 5×10 15 cm -3 A P-type Si sheet as a substrate;
[0322] (1b) Thermally oxidize a layer of SiO with a thickness of 500nm on the surface of the substrate 2 layer;
[0323] (1c) Photoetching the buried layer region, implanting N-type impurities into the buried layer region, and annealing at 950° C. for 30 minutes to activate the impurities to form an N-type heavily doped buried layer region.
[0324] Step 2, deep trench isolation preparation.
[0325] (2a) Remove the redundant oxide layer on the surface, and epitaxially grow a layer of N-type epitaxial Si layer 4 with a thickness of 2 μm, as the collector region, and the doping concentration of this layer...
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