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Method for testing EEPROM (electrically erasable programmable read-only memory) read-write cycle times

A technology of read-write cycle and test method, which is applied in the field of test, can solve problems such as device misjudgment, long writing and erasing time, inability to read and write cycle time, etc., and achieve the effect of reducing requirements and flexible testing

Active Publication Date: 2015-04-01
湖北航天技术研究院计量测试技术研究所
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, EEPROM implements writing and erasing operations through electronic transitions. Since the time required for electronic transitions is relatively long, the writing and erasing time of EEPROM is relatively long. Generally, the writing and erasing time of a byte is 200μs~ 10ms, and the writing and erasing time of the whole device is usually more than 1000ms, so it is impossible to test the EEPROM by using the algorithmic graphic test method commonly used in random access memory, and can only refer to the read-only memory ROM for the read operation test of the empty chip and the DC Parameter test, but cannot test the read and write cycle time, and cannot detect typical faults such as too long writing time, which may easily cause misjudgment of the device

Method used

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  • Method for testing EEPROM (electrically erasable programmable read-only memory) read-write cycle times
  • Method for testing EEPROM (electrically erasable programmable read-only memory) read-write cycle times
  • Method for testing EEPROM (electrically erasable programmable read-only memory) read-write cycle times

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0039] Tested object: EEPROM device X28C64DMB-20VI produced by XICRO Company, the write cycle time t specified in its detailed specification WC The maximum value is 10ms, the read cycle time t RC The minimum value of 200ns, a total of 64 pages of 64 memory cells per page.

[0040] Test method: follow the steps below:

[0041] a. Write test pattern vector;

[0042] a11. According to the size of the tested EEPROM "page write" and the capacity of the test system's graphic generator, set the written graphic vector to the first 2 3 A page is a write operation graphic vector and a read operation graphic vector of a total of 512 storage units in 8 pages;

[0043] a12. Select the first page storage unit;

[0044] a13. Set background data 0xaa;

[0045] a14. According to the write cycle time t specified in the detailed specification of the device WC The maximum value and the actual running speed are 1000ns, and the number of cycles is set to 10000 times;

[0046] a15. Send write...

Embodiment 2

[0067] Tested object: same as embodiment 1

[0068] Test method: in the scheme recorded in embodiment 1, after step b6, if the write cycle time test of the device under test is qualified, erase the memory and gradually reduce t WC value, repeat steps b1~b5, when t WC = t n-1 = 8.1ms write cycle time test is still qualified, but until t WC = t n = 8ms when the test result is reversed, then t n-1 =8.1ms is the specific value of the tested EEPROM write cycle time.

Embodiment 3

[0070] Measured object: same as embodiment 2

[0071] Test method: in the scheme recorded in embodiment 2, after step c6, the read cycle time test of the device under test is qualified, gradually reducing t RC value, repeat steps c3~c5, when t RC = t n-1 = 191ms write cycle time test is still qualified, but until t RC = t n = 190ns when the test result is reversed, then t n-1 =191ns is the specific value of the measured EEPROM read cycle time.

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Abstract

The invention relates to a method for testing electrically erasable programmable read-only memory (EEPROM) read-write cycle times. The method comprises the following steps of: compiling write operation graph vectors and read operation graph vectors of storage units in previous 2n (n is greater than or equal to 0 and less than or equal to 5) pages; running the write operation graph vectors, performing write operations on the storage units, and testing write cycle times; and running the read operation graph vectors, performing read operations on the storage units, and testing read cycle times. In the method, partial test graph vectors are used for reducing requirements for a test system, and a high address wire bit-by-bitantiphase method is used for switching all storage units, so that tests of the EEPROM read-write cycle times go deep into each unit, thus realizing the tests of all unit-by-unit read-write cycle times without large graph vector storage space, and being beneficial to performing a return-to-zero analysis for engineering quality. By adopting the method, the EEPROM read-write cycle times can be tested comprehensively, accurately, conveniently and flexibly.

Description

technical field [0001] The invention relates to a test method, in particular to a test method for EEPROM read and write cycle time. Background technique [0002] As a non-volatile memory, EEPROM is widely used in single-chip microcomputers and other occasions that require high data storage security and reliability, such as access control and attendance systems, measurement and medical instruments, contactless smart cards, tax control cash registers, Prepaid watt-hour meters or multi-rate watt-hour meters, home appliance remote controls, etc. However, EEPROM implements writing and erasing operations through electronic transitions. Since the time required for electronic transitions is relatively long, the writing and erasing time of EEPROM is relatively long. Generally, the writing and erasing time of a byte is 200μs~ 10ms, and the writing and erasing time of the whole device is usually more than 1000ms, so it is impossible to test the EEPROM by using the algorithmic graphic ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G11C29/56
Inventor 袁云华李永梅王炳军
Owner 湖北航天技术研究院计量测试技术研究所