Semiconductor device and manufacturing method thereof

Abstract

The invention relates to a semiconductor device and a manufacturing method thereof. The semiconductor device comprises a gate structure, germanium containing semiconductor layers and a doped epitaxial semiconductor layer, wherein the gate structure is positioned on a substrate; the germanium containing semiconductor layers are positioned on two sides of the gate structure; the doped epitaxial semiconductor layer epitaxially grows between the germanium containing semiconductor layers; and bottom surfaces of the germanium containing semiconductor layers and the epitaxial semiconductor layer are positioned on the same horizontal plane, wherein the epitaxial semiconductor layer is used as a channel region; and the germanium containing semiconductor layers are used as source and drain extension regions; according to the invention, shallow junction depths (or small thickness) and high doping concentration of the source and drain extension regions can be advantageously achieved.

Description

technical field [0001] The present invention relates to a semiconductor device and a method of manufacturing the same. In particular, the present invention relates to semiconductor devices with epitaxial source and drain extensions and methods of manufacturing the same. Background technique [0002] Currently, millions of semiconductor devices are integrated to form very large scale integrated circuits. [0003] figure 1 A cross-sectional view of a conventional semiconductor device (transistor) is shown. A transistor generally includes a gate dielectric layer 140 on a semiconductor substrate (not shown here for simplicity) and a gate layer 150 on the gate dielectric layer 140 . Sidewall spacers 160 and 165 are formed on sidewalls of the gate dielectric layer 140 and the gate layer 150 . The transistor also generally includes a pair of source and drain regions 110 substantially aligned with the outer edges of the sidewall spacers 165 . In addition, a pair of source-drain...

AI Technical Summary

Problems solved by technology

[0006] However, the inventors of the present invention have carried out in-depth research on this and found that the junction depth and active dopant concentration of the source and drain extension regions formed by ion implantation and laser melting / sub-melting annealing need to be further improved

Incidentally, although SIMS (Secondary Ion Mass Spectrometry) is commonly used to measure the dopant distribution after laser melting / submelting annealing, SIMS cannot tell whether the dopant is activated or not

Images