Superjunction device and method of manufacturing the same

A super-junction device and charge technology, applied in the field of semiconductor integrated circuit manufacturing, can solve problems such as poor softness factor

Active Publication Date: 2020-12-11
SHENZHEN SANRISE TECH CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

However, since the P+ contact region in the P-type ring in the transition region is also very dense, the ability to collect holes under the forward Vds is very strong, so the process of the body diode of the device from normal conduction to reverse bias is immediate During the reverse recovery process, since the holes are quickly drawn out through the P+ region through the contact hole, the reverse recovery is very fast and the softness factor is poor

Method used

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  • Superjunction device and method of manufacturing the same
  • Superjunction device and method of manufacturing the same
  • Superjunction device and method of manufacturing the same

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no. 1 example approach

[0118] The manufacturing method of the super junction device according to the first embodiment of the present invention is to manufacture such as Figure 4 The superjunction device of the first embodiment of the present invention is shown as an example for description, as Figure 8A to Figure 8H Shown is a schematic cross-sectional view of the device in each step of the manufacturing method of the super-junction device in the first embodiment of the present invention; in the manufacturing method of the super-junction device in the embodiment of the present invention, the middle region of the super-junction device is the charge flow region, that is, region 1, Termination zone, that is, zone 3, surrounds the periphery of the charge flow region, and transition zone, that is, zone 2, is located between the charge flow zone and the terminal zone; the structure of the top view of the superjunction device can also refer to figure 1 shown. The method of the first embodiment of the pr...

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Abstract

The invention discloses a super-junction device, which is characterized in that a protective epoxy film exposes a charge flow region, completely covers a transition region and completely or mostly covers a terminal region, a second contact hole at the top of a P-type ring of the transition region is enabled to penetrate deeper than a first contact hole at the top of a P-type well of the charge flow region by the thickness of one protective epoxy film, and thus the junction depth of a second P+ contact region at the bottom of the second contact hole is enabled to be less than the junction depthof a first P+ contact region at the bottom of the first contact hole, so that the distance between a hole collected by the P-type ring to the second P+ contact region, and a softness factor of reverse recovery of a body diode of the device is increased. The invention further discloses a manufacturing method of the super-junction device. According to the invention, the reverse recovery characteristics of device can be improved, and the avalanche tolerance of the device is enhanced at the same time.

Description

technical field [0001] The invention relates to a method for manufacturing a semiconductor integrated circuit, in particular to a method for manufacturing a superjunction device. Background technique [0002] The super junction structure is composed of alternately arranged N-type pillars and P-type pillars. If the superjunction structure is used to replace the N-type drift region in the vertical double-diffused MOS transistor (Vertical Double-diffused Metal-Oxide-Semiconductor, VDMOS) device, the conduction path is provided through the N-type column in the conduction state, and when the conduction The P-type column does not provide a conduction path; in the off state, the PN column jointly bears the reverse bias voltage, forming a super-junction metal-oxide-semiconductor field-effect transistor (Metal-Oxide-Semiconductor Field-Effect Transistor, MOSFET). The super-junction MOSFET can greatly reduce the on-resistance of the device by using a low-resistivity epitaxial layer w...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L29/06H01L21/336H01L29/78
CPCH01L29/0611H01L29/0615H01L29/0684H01L29/66477H01L29/78
Inventor 肖胜安曾大杰李东升
Owner SHENZHEN SANRISE TECH CO LTD
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