Multiprocessor inter-core transmission method for avoiding data back writing during read-miss

A multi-processor core and transmission method technology, which is applied in the direction of electrical digital data processing, instruments, memory systems, etc., can solve the problem of invalid cache copy content, achieve the effect of reducing the number of times and improving system performance

Active Publication Date: 2013-01-30
C SKY MICROSYST CO LTD
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  • Summary
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  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Under such an architecture, the problem of cache data consistency is an important issue that has always plagued designers.
[0005] 1. Invalid state: the content of the cache copy is invalid;

Method used

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  • Multiprocessor inter-core transmission method for avoiding data back writing during read-miss
  • Multiprocessor inter-core transmission method for avoiding data back writing during read-miss
  • Multiprocessor inter-core transmission method for avoiding data back writing during read-miss

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Experimental program
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Embodiment Construction

[0026] The present invention will be further described below in conjunction with the accompanying drawings.

[0027] refer to figure 1 , a multi-processor inter-core transfer method that avoids data write-back when read misses occur. When read misses occur, data that supports cache valid dirty copies (cache valid copies different from main memory data) is directly transferred between processors , without first writing the data of the valid dirty copy of the cache back to the main memory; it supports a main memory block to have multiple valid dirty copies, and multiple valid dirty copies are written back to the main memory at most once; a kind of MESI protocol is adopted as a cache coherency protocol.

[0028] A MESI-like protocol is adopted as the cache coherency protocol. This protocol is suitable for caches with a write-return strategy. In this protocol, each cache copy has four states: invalid state, shared state, exclusive state, and modified state. The states are define...

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Abstract

The invention relates to a multiprocessor inter-core transmission method for avoiding data back writing during read-miss. Each high-speed cache copy has four states including an invalid state, a shared state, a monopolized state and a modifying state. Each high-speed cache copy has three status bits including an effective bit, a shared bit and a back writing bit, wherein the effective bits indicate whether the high-speed cache copies are valid, the shared bits indicate whether the high-speed cache copies are in a shared state, and the back writing bits indicate whether valid high-speed cache copies are needed to be written back when removed from a cache; and the transmission method supports indirect transmission of high-speed cache valid dirty copies among processors, and the high-speed cache valid dirty copies refer to high-speed cache valid copies which are different from main storage data. According to the multiprocessor inter-core transmission method for avoiding data back writing during read-miss, a main storage is provided for avoiding data back writing during read-miss effectively, access times of the main storage by the processor are effectively reduced, and the system performance is enhanced.

Description

technical field [0001] The invention relates to the technical field of multi-processor inter-core transmission, in particular to a multi-processor inter-core transmission method. Background technique [0002] With the continuous improvement of human's demand for computer speed and computing scale, traditional single-core processors can no longer meet the needs of the market, and multi-core processors have emerged as the times require. At the same time, with the improvement of integrated circuit manufacturing technology, the integration of multi-core on a single chip has become a reality. The multi-processor system that was originally used only on large servers has gradually entered the general consumer market. More and more embedded systems are Using multi-core chips. A multi-level cache memory architecture is generally used in a multi-core architecture to improve processor efficiency. Under such an architecture, cache cache data consistency is an important issue that has ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/08G06F13/16G06F12/0868
Inventor 严晓浪余慜黄凯葛海通
Owner C SKY MICROSYST CO LTD
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