Multi-core processor system and cache coherency processing method

A technology of a multi-core processor and a processing method, applied in the computer field, can solve the problems of poor performance of multi-core processor system and high possibility of memory, etc.

Active Publication Date: 2015-10-21
INSPUR BEIJING ELECTRONICS INFORMATION IND
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Problems solved by technology

[0005] In order to solve the above-mentioned technical problems, the present invention provides a multi-core processor system and a cache coherency processing method to solve the problem that the memory i

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  • Multi-core processor system and cache coherency processing method
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Embodiment Construction

[0062] In order to make the purpose, technical solution and advantages of the present invention more clear, the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings. It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined arbitrarily with each other.

[0063] The steps shown in the flowcharts of the figures may be performed in a computer system, such as a set of computer-executable instructions. Also, although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that shown or described herein.

[0064] The cache lines in the multi-core processor system provided by the following embodiments of the present invention all have an M state, an exclusive (Exclusive, abbreviated as: E) state, a keeping (Keeping, abbreviated as: K) state, and an invalid (I...

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Abstract

The invention discloses a multi-core processor system and a cache coherency processing method, wherein the multi-core processor system provided herein is used for executing cache coherency processing; the cache line in the multi-core processor system has M, E, K, I, and F states; a first processor core is used for sending first request message asking for read operations to a second processor core; the second processor core is used for sending datum carried in first response message in a first cache line to the first processor core and the second processor core is used for changing the state of the first cache line to the K state; and after the state of the first cache line is changed from the M state to the K state, the second processor core will neglect the operations of writing the datum of the first cache line into memory. According to the invention, when the cache coherency processing is executed by the multi-core processor system in the existing technology, the problem of poor performance of the multi-core processor system due to high possibility of the memory to participate in the processing is solved.

Description

technical field [0001] The invention relates to computer technology, in particular to a multi-core processor system and a cache consistency processing method. Background technique [0002] Each processor core of a multi-core processor system usually maintains cache coherence according to a cache coherence protocol. The cache coherence protocol directly affects the data access performance of the multi-core processor system, and then affects the overall performance of the multi-core processor. [0003] Currently commonly used cache coherence protocols include the MESIF protocol and the MOESI protocol. On the one hand, the MESIF protocol introduces the forwarding (Forwarding, referred to as: F) state in the MESI protocol, and there are multiple shared (Shared, referred to as: S) state cache lines in the multi-core processor system, and at this time there is a processor When the kernel requests to read the data in these S-state cache memory (cache) rows, the state of one of the...

Claims

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Application Information

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IPC IPC(8): G06F12/08
Inventor 王恩东倪璠陈继承
Owner INSPUR BEIJING ELECTRONICS INFORMATION IND
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