Method for aligning semiconductor materials

Abstract

OF THE DISCLOSUREMETHOD FOR ALIGNING OF SEMICONDUCTOR WAFERDisclosed herein is a method for accurately aligning the position of a semiconductor wafer to accurately transfer the semiconductor wafer to aprocessing position in an apparatus for manufacturing a semiconductor package.That is, the present invention provides a method for aligning a semiconductor wafer, implemented in a wafer treatment apparatus such as a singulation apparatus that cuts a semiconductor wafer, on which a plurality ofsemiconductor packages are arranged in a matrix form, into each semiconductor package, the method characterized in that a vision camera photographs an arrangement relationship between the center of a dowel hole and that of the semiconductor package to accurately determine the position of the wafer in the X-, Y-, and [Theta] directions, thus accurately transferring the wafer toa processing position. Therefore, the method of the present invention can be effectively applied to a method for aligning a new type of wafer such as a wafer-level package. Especially, the method of the present invention can minimize the effect of errors due to vibration of the apparatus, etc. and obtain an accurate measurement value, thus accurately aligning the position of the wafer.Fig. 10

Description

[0001] Cross References to Related Applications [0002] This application is claimed under 35 U.S.C. §119(a) to Korean Patent Application No. 10-2010-0041973 filed May 4, 2010 and Korean Patent Application No. 10-2010-0048752 filed May 25, 2010 interests, the entire contents of which are hereby incorporated by reference. technical field [0003] The present invention relates to a method of aligning the position of a semiconductor wafer, and more particularly, to a method of precisely aligning the position of a semiconductor wafer for precise transfer of the semiconductor wafer to a processing location in an apparatus for manufacturing semiconductor packages. Background technique [0004] Generally, a semiconductor package is manufactured in such a manner that a plurality of semiconductor packages on which transistors and capacitors are integrated at a high density are attached to a rectangular plate-shaped lead frame, and the plurality of semiconductor packages are electrica...

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Problems solved by technology

[0007] However, when the wafer to be subjected to the dicing process has a circular shape, such as wafer-level packaging, it is difficult to precisely coincide the dicing line of the wafer with the blade receiving groove on the chuck table, so that the wafer is transferred to the card during the singulation process. The wafer may not be placed precisely on the chuck table when the position of the dicing process on the chuck table

[0008] Thus, if the wafer is not placed precisely on the chuck table for dicing, the cutting line of the wafer does not exactly coincide with the blade receiving slot on the chuck table, and the tip of the dicing blade may hit the edge of the chuck table during the dicing process. Top surface, damage to expensive cutting blades or chuck tables

[0009] In addition, the wafer will not be diced into a desired shape along the dicing lines forming the matrix shape, and the semiconductor package is judged to be defective, which increases manufacturing cost and significantly lowers productivity

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