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Processor using interrupt signal to define instruction decoding

A technology for selecting circuits and operation codes, which is applied in the direction of electrical digital data processing, multi-channel program devices, program control design, etc., and can solve the problems of increasing the scale of processor circuits and increasing the number of bits

Inactive Publication Date: 2013-03-06
CYPRESS SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, this requires an increase in the number of bits representing instruction codes, and therefore, a significant increase in the circuit scale of the processor

Method used

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  • Processor using interrupt signal to define instruction decoding
  • Processor using interrupt signal to define instruction decoding
  • Processor using interrupt signal to define instruction decoding

Examples

Experimental program
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Embodiment Construction

[0028] figure 2 is a schematic configuration diagram of the hardware outline of the computer of the first embodiment.

[0029] The computer of the first embodiment has a processor 31, an instruction memory 21, a data memory 22, and a dedicated processing arithmetic unit 23 for processing additional instructions. The processor 31 has an instruction decoding unit 32 , an arithmetic unit 33 , a register file 34 , a data transmission module 35 and an interrupt register (REG) 36 . The instruction decoding unit 32 has an additional instruction decoder 42 .

[0030] Processors that receive interrupt signals generated inside and outside of chips including semiconductor processing devices are known. The processor 31 branches to the interrupt handler and performs interrupt processing in response to an interrupt signal, and returns to initial processing by a return (RETI) instruction when the interrupt processing is completed. Interrupt signals have a multi-interrupt structure in whi...

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PUM

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Abstract

A processor includes: an arithmetic unit configured to execute instructions; an instruction decode part configured to decode the instructions executed in the arithmetic unit and to output opcodes; and an interrupt register configured to receive interrupt signals, wherein the instruction decode part includes an instruction code map that stores the opcodes in correspondence to instructions and outputs the opcodes in accordance with the instructions inputted, and the instruction code map stores a plurality of sets of opcodes to be output as switch opcodes corresponding to additional instructions, the additional instructions are a part of the instructions, and switches the sets of the switch opcodes in accordance with the interrupt signal.

Description

technical field [0001] The embodiments discussed herein relate to processors. Background technique [0002] In recent years, semiconductor processing devices including processors (CPUs) are widely used. For example, in an automobile, about 100 semiconductor processing devices are installed. As a semiconductor processing device for a specific application, a general-purpose semiconductor processing device is used from the viewpoint of cost. In actual use of a semiconductor processing apparatus, specialized processing in a specific application is repeatedly performed in many cases, and specific instructions are frequently executed. Therefore, in order to quickly respond to requests, user applications are optimized, using a semiconductor processing device including a processor to which dedicated instructions are added for each application. In such processors, a method is generally used in which a dedicated interface is provided for additional instructions, and dedicated opcod...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F9/30G06F9/48
CPCG06F9/30196G06F9/3822G06F9/3861G06F9/30181G06F9/30G06F9/30003
Inventor 辻雅之
Owner CYPRESS SEMICON CORP