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Reversible master-slave RS flip-flop based on reversible logical gate
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A flip-flop and logic gate technology, applied in logic circuits, pulse generation, electrical components, etc., can solve the problems of less garbage bits and low quantum cost
Inactive Publication Date: 2013-03-20
SHANGHAI UNIV OF ENG SCI
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[0013] The present invention aims at the defects of existing reversible master-slave RS flip-flops, and provides a reversible master-slave RS flip-flop based on reversible logic gates with small quantum cost and few garbage bits
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Embodiment 1
[0046] Such as Figure 9 Shown, the present invention comprises:
[0047] First Peres Gate 2;
[0048] The second Peres gate 3, the first output end of the first Peres gate 2 is connected to the first input end of the second Peres gate 3;
[0049] The main reversible flip-flop 7, the third output terminals of the first Peres gate 2 and the second Peres gate 3 are respectively connected to the two input terminals of the main reversible flip-flop 7
[0050] The third Peres gate 5, the first output end of the main reversible flip-flop 7 is connected to the second input end of the third Peres gate 5;
[0051]The fourth Peres gate 6, the first output end of the third Peres gate 5 is connected to the first input end of the fourth Peres gate 6; the second output end of the main reversible flip-flop 7 is connected to the second input end of the fourth Peres gate 6;
[0052] From the reversible flip-flop 8, the third output of the third Peres gate 5 and the fourth Peres gate 6 are...
Embodiment 2
[0064] Such as Figure 11 Shown is another embodiment of the present invention. Include:
[0065] First Peres Gate 2;
[0066] The second Peres gate 3, the first output end of the first Peres gate 2 is connected to the first input end of the second Peres gate 3;
[0067] The main reversible flip-flop 7, the third output terminals of the first Peres gate 2 and the second Peres gate 3 are respectively connected to the two input terminals S and R of the main reversible flip-flop 7;
[0068] The third Peres gate 5, the first output end of the main reversible flip-flop 7 is connected to the second input end of the third Peres gate 5;
[0069] The fourth Peres gate 6, the first output end of the third Peres gate 5 is connected to the first input end of the fourth Peres gate 6; the second output end of the main reversible flip-flop 7 is connected to the second input end of the fourth Peres gate 6;
[0070] From the reversible flip-flop 8 , the third output terminals of the third ...
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Abstract
The invention relates to a reversible master-slave RS flip-flop based on a reversible logical gate. The reversible master-slave RS flip-flop comprise a first Peres gate, a second Peres gate, a reversible master flip-flop, a third Peres gate, a fourth Peres gate, and a reversible slave flip-flop, wherein a first output end of the first Peres gate is connected with a first input end of the second Peres gate; third output ends of the first Peres gate and the second Peres gate are connected with two input ends of the reversible master flip-flop respectively; a first output end of the reversible master flip-flop is connected with a second input end of the third Peres gate; the first output end of the third Peres gate is connected with a first input end of the fourth Peres gate; a second output end of the reversible master flip-flop is connected with a second input end of the fourth Peres gate; and third output ends of the third Peres gate and the fourth Peres gate are connected with the two input ends of the reversible slave flip-flop respectively. The reversible master-slave RS flip-flop has low quantum cost, few quantum gates, few junk digits and outstanding performances.
Description
technical field [0001] The invention relates to a reversible logic circuit with low power consumption in the information field, in particular to a reversible master-slave RS flip-flop based on the replacement of reversible logic gates and the reuse of garbage bits. Background technique [0002] Traditional irreversible circuits consume energy due to the erasure of information. At room temperature, although the energy loss is very small, it cannot be ignored for low-power circuit design. At the same time, the heat generated by energy consumption also affects the chip integration and the running speed of the computer. [0003] The reversible circuit is composed of reversible logic gates, the input and output bits are equal, the corresponding truth table satisfies the one-to-one mapping function, and the input and output are reversible. [0004] Theoretically, the reversible circuit does not lose input information, and there is no heat dissipation, which effectively solves the...
Claims
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