Reversible master-slave RS flip-flop based on reversible logical gate
A flip-flop and logic gate technology, applied in logic circuits, pulse generation, electrical components, etc., can solve the problems of less garbage bits and low quantum cost
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Embodiment 1
[0046] Such as Figure 9 Shown, the present invention comprises:
[0047] First Peres Gate 2;
[0048] The second Peres gate 3, the first output end of the first Peres gate 2 is connected to the first input end of the second Peres gate 3;
[0049] The main reversible flip-flop 7, the third output terminals of the first Peres gate 2 and the second Peres gate 3 are respectively connected to the two input terminals of the main reversible flip-flop 7
[0050] The third Peres gate 5, the first output end of the main reversible flip-flop 7 is connected to the second input end of the third Peres gate 5;
[0051]The fourth Peres gate 6, the first output end of the third Peres gate 5 is connected to the first input end of the fourth Peres gate 6; the second output end of the main reversible flip-flop 7 is connected to the second input end of the fourth Peres gate 6;
[0052] From the reversible flip-flop 8, the third output of the third Peres gate 5 and the fourth Peres gate 6 are...
Embodiment 2
[0064] Such as Figure 11 Shown is another embodiment of the present invention. Include:
[0065] First Peres Gate 2;
[0066] The second Peres gate 3, the first output end of the first Peres gate 2 is connected to the first input end of the second Peres gate 3;
[0067] The main reversible flip-flop 7, the third output terminals of the first Peres gate 2 and the second Peres gate 3 are respectively connected to the two input terminals S and R of the main reversible flip-flop 7;
[0068] The third Peres gate 5, the first output end of the main reversible flip-flop 7 is connected to the second input end of the third Peres gate 5;
[0069] The fourth Peres gate 6, the first output end of the third Peres gate 5 is connected to the first input end of the fourth Peres gate 6; the second output end of the main reversible flip-flop 7 is connected to the second input end of the fourth Peres gate 6;
[0070] From the reversible flip-flop 8 , the third output terminals of the third ...
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