Achieving method of low-delay multimedia access controller (MAC)/ physical coding subsystem (PCS) framework of Ethernet and device thereof

Abstract

The invention provides a low-delay multimedia access controller (MAC) / physical coding subsystem (PCS) framework of the Ethernet and an achieving method thereof. Data transmitting includes transmitting direction and receiving direction. The method includes defining a deserializing clock domain and a user clock domain, conducting cross clock domain processing from the user clock domain to the deserializing clock domain in the data transmitting direction and conducting cross clock domain processing from the deserializing clock domain to the user clock domain in the data receiving direction. The framework and the method reduce transmitting delay fo network data in a MAC / PCS layer in the way that only one cross clock domain is arranged in the MAC / PCS transmitting direction and receiving direction. Further, the framework and the method adopt an elastic buffer to achieve clock compensation and are low in cost.

Description

technical field [0001] The invention relates to the field of Ethernet, in particular to a method and a device for realizing the low-latency MAC / PCS architecture of the Ethernet. Background technique [0002] With the development of Ethernet technology, in order to meet the needs of data transmission at different rates, IEEE802.3 defines a variety of interfaces, such as XGMII (10G media independent interface), XLGMII (40G media independent interface), CGMII (100G media independent interface) etc., so that the MAC (Media Access Controller) and PCS (Physical Coding Layer) modules provided by different manufacturers can work together. At present, in the general 10G / 40G / 100G Ethernet MAC / PCS design, according to the architecture defined in IEEE802.3, the MAC and PCS layers are designed separately, and the standard XGMII / XLGMII / CGMII interface is used to connect the above two functions module. [0003] figure 1 It is a schematic diagram of the data transmission mode of 10G / 40G / ...

AI Technical Summary

Problems solved by technology

Among them, no matter it is the receiving direction or the sending direction, since there may be a certain error between the two different clock domains, an elastic buffer (elastic FIFO) needs to be inserted between the serdes clock domain and the XGMII / XLGMII / CGMII interface clock domain to complete Clock compensation, however, this method will inevitably increase the transmission delay of packets in MAC / PCS

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