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32results about How to "Eliminate transmission delays" patented technology

Gas jet flow type blue adding combined ejector and application thereof

InactiveCN106150612AReduce riskEliminate transmission delayExhaust apparatusSilencing apparatusEngineeringLiquid phase
The invention discloses a gas jet flow type blue adding combined ejector. The ejector comprises a double-layer casing pipe, a blue adding channel is formed in a pipe side of the double-layer casing pipe, a compression air channel is formed in a shell side, and the blue adding channel and the compression air channel are coaxial and are isolated from each other; a pneumatic nozzle is formed in the front end of the double-layer casing pipe and comprises a nozzle shell, a casing pipe joint and a rotary flow core; an annular nozzle gas phase channel is formed between the nozzle shell and the rotary flow core, a nozzle liquid phase channel is formed in the rotary flow core, and the two channels are communicated with the front end of the blue adding channel and the front end of the compression air channel correspondingly; the outlet end of the nozzle gas phase channel is provided with a compression air ring line outlet, and the outlet end of the nozzle liquid phase channel is provided with a blue adding ejecting hole; the rear end of the compression air channel is sealed, a compression air inlet pipe is arranged on the rear portion of the compression air channel, and a compression air inlet is formed in the compression air inlet pipe; a blue adding inlet is formed in the rear end of the blue adding channel. According to the ejector, compression air is used for serving as a blue adding ejecting power source, and pump-free quantitative ejecting of added blue is achieved.
Owner:WUHAN UNIV OF TECH +1

Novel driving system and control device of servo press

PendingCN112810226AEliminate gapsRealize synchronous independent control functionForging press drivesPressesKinematic controllerGear wheel
The invention relates to the technical field of forging machines and motor control, in particular to a novel driving system and control device of a servo press. The novel driving system and control device of the servo press comprises a servo press external input signal, a human-computer interaction interface, a motion control function module, a high-level protocol stack COE, a TCP / IP protocol stack, an instruction analysis module, a ucos II embedded operating system, a motor control state machine, a motor control module, a current signal conditioning circuit, a position signal conditioning circuit, a fault protection module, a PWM module, other functional hardware, a power driving circuit, a six-phase full-bridge IGBT module, two three-phase linear motors, position sensors of the two three-phase linear motors, sampling circuits and a sliding block, wherein the current signal conditioning circuit, the position signal conditioning circuit, the fault protection module and the PWM module belong to hardware. According to the technical scheme, a motion controller and two servo controllers are integrated, communication delay is eliminated, a gear is omitted, a gap is eliminated, and the control precision of the position of the sliding block is improved; and due to the fact that the two motors are adopted for independent control, closed-loop real-time control over left-right balance of the sliding block can be achieved.
Owner:JINING KELI PHOTOELECTRIC IND CO LTD +1

Coding and decoding method, related devices and related communication system

An embodiment of the invention discloses a coding and decoding method, related devices and a related communication system. The scheme includes that coding and decoding between two information sources are supported by a DNCP (dynamic host configuration protocol), a coding device performs random linear coding for two IP (internet protocol) data packets with the arrival interval shorter than a set duration and identical target addresses, and accordingly influence of the problem of mismatching of transmission delays, sending rates and the like in an actual network is advantageously eliminated to a certain degree; DNCP packet headers of DNCP data packets carry two information source identities, two IP data packet identities and coding coefficient and vector information related to coding coefficients and vectors, accordingly, a foundation is laid for the coding device to continue repeated coding or a decoding device to quickly decode, and the universality of network coding in the actual network is improved advantageously; and as the coding and decoding method, the related devices and the communication system are implemented on the basis of a network coding technology, network resources can be sufficiently utilized, the throughput rate of the network is obviously increased, and high transmission efficiency is achieved.
Owner:HONOR DEVICE CO LTD

Multichip synchronization structure based on time-digital converter circuit

The invention discloses a multichip synchronization structure based on a time-digital converter circuit. The multichip synchronization structure comprises N circuit chips provided with built-in time-digital converters and time sequence regulation modules. Each chip contains a synchronization indicating signal receiving end, a synchronization indicating signal output end, one time-digital converter and one time sequence regulation module, wherein the synchronization indicating signal receiving end is used for receiving a synchronization indicating signal input into the chip externally; the synchronization indicating signal output end is used for outputting a synchronization indicating signal subjected to time sequence resampling through a trigger in the chip, wherein the sampling frequency of the trigger is completely aligned with a time sequence of a maximum frequency clock; the time-digital converter is used for quantizing time sequence delays of two input signals into digital values, wherein the input signal IN1 is the synchronization indicating signal input into the chip externally, and the input signal IN2 is the synchronization indicating signal subjected to time sequence resampling through the trigger in the chip; and the time sequence regulation module is used for regulating output delays of the synchronization indicating signals according to the input digital values. By the adoption of a daisy chain structure, the load on a synchronization indicating signal source is relieved.
Owner:NO 24 RES INST OF CETC

A tracking target selection synchronization method for patrol drones

The invention discloses a tracking target selection synchronization device and method for a cruise unmanned aerial vehicle. The device includes an airborne tracking platform and a monitoring terminal. The airborne tracking platform includes a main controller, an image wireless sending module, a first data communication module and the first image cache module, the input terminal of the main controller is connected with a video acquisition module, and the monitoring terminal includes a monitoring computer, a man-machine interface operation module, an image wireless receiving module, a second data communication module and a second image Buffering module; the method includes the following steps: one, video image collection and transmission to the monitoring computer; two, tracking target selection and information upload to the airborne tracking platform; three, the airborne tracking platform judges and completes the tracking target selection synchronization, and completes the tracking Target selection initialization. The invention has a reasonable design, can accurately obtain the initial tracking target selected by the monitoring terminal of the ground station, and realizes the synchronization of the tracking target selection of the patrol drone and the monitoring terminal.
Owner:ROCKET FORCE UNIV OF ENG

Frame signaling transmission method based on power multiplexing

The invention belongs to the technical field of wireless data transmission and signal processing, and particularly relates to a frame signaling transmission method based on power multiplexing, which is used for a transmission system using a variable modulation coding / adaptive modulation coding system. The method comprises the following steps: carrying out specific modulation mapping on a physical layer signaling code PLSC of a transmission frame to form a physical layer signaling symbol sequence of the transmission frame, carrying out repeated coding on the physical layer signaling symbol sequence of the next transmission frame, and adding a filling symbol to obtain a signaling transmission sequence of the next transmission frame; enabling the signaling transmission sequence of the next transmission frame and the data symbol of the current frame to be transmitted in parallel in the same channel by using power distribution and power domain superposition coding; when the receiving end obtains the data symbol of the current frame, the receiving end obtains the physical layer signaling code of the next transmission frame in parallel, so that the parameter information of the coding modulation combination of the next frame is obtained in advance, the receiving end carries out corresponding configuration on a data demodulator and a decoder in time, and the continuity of receiving, demodulating and decoding is kept.
Owner:NAT SPACE SCI CENT CAS

A Multi-chip Synchronization Architecture Based on Time-to-Digital Converter Circuit

The invention discloses a multichip synchronization structure based on a time-digital converter circuit. The multichip synchronization structure comprises N circuit chips provided with built-in time-digital converters and time sequence regulation modules. Each chip contains a synchronization indicating signal receiving end, a synchronization indicating signal output end, one time-digital converter and one time sequence regulation module, wherein the synchronization indicating signal receiving end is used for receiving a synchronization indicating signal input into the chip externally; the synchronization indicating signal output end is used for outputting a synchronization indicating signal subjected to time sequence resampling through a trigger in the chip, wherein the sampling frequency of the trigger is completely aligned with a time sequence of a maximum frequency clock; the time-digital converter is used for quantizing time sequence delays of two input signals into digital values, wherein the input signal IN1 is the synchronization indicating signal input into the chip externally, and the input signal IN2 is the synchronization indicating signal subjected to time sequence resampling through the trigger in the chip; and the time sequence regulation module is used for regulating output delays of the synchronization indicating signals according to the input digital values. By the adoption of a daisy chain structure, the load on a synchronization indicating signal source is relieved.
Owner:NO 24 RES INST OF CETC
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