Check patentability & draft patents in minutes with Patsnap Eureka AI!

High dynamic range sub-sampling architecture

A technology of high dynamic range and pixel array, which is applied in the direction of TV, color TV parts, TV system parts, etc., and can solve the problem of full well

Active Publication Date: 2013-04-17
OMNIVISION TECH INC
View PDF3 Cites 11 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Current charge-coupled devices (CCDs) and CMOS sensors cannot achieve this range due to full well limitations and noise floor limitations typically around 60~70dB

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • High dynamic range sub-sampling architecture
  • High dynamic range sub-sampling architecture
  • High dynamic range sub-sampling architecture

Examples

Experimental program
Comparison scheme
Effect test

Embodiment approach

[0072] Pixel Implementation, Row Drivers, and Timing

[0073] figure 2 An example of a pixel array in a multi-row simultaneous readout scheme according to an embodiment of the present invention is illustrated. exist figure 2 In the embodiment in , two shared non-row selection pixels are used as an example. In other embodiments, other pixel structures and variations may be used. One logical unit cell 109 (outlined with a dotted line) contains two pixels that have the same row decoder address (e.g., row ) and share the same row driver signal, the same transmit (TX) line, and the same reset (RST) and set (RS) signals.

[0074] exist figure 2 , pixels are arranged in two columns (for example, columns C1 and C2 ) and six rows (for example, rows R1 , R2 . . . R6 ). The illustrated embodiment of each pixel circuit includes a photodiode PD, transfer transistor Tl, reset transistor T2, and select transistor T3. During operation, transfer transistor T1 receives a tran...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

A system, method and apparatus implementing a multiple-row concurrent readout scheme for high-speed CMOS image sensor with backside illumination are described herein. In one embodiment, the method of operating an image sensor starts acquiring image data within a color pixel array and the image data from a first set of multiple rows in the color pixel array is then concurrently readout. Concurrently reading out the image data from the first set of multiple rows includes concurrently selecting a first portion of the image data from the first set by first readout circuitry and a second portion of the image data from the first set by second readout circuitry. The first and second portions of the image data from the first set are different and the first and second readout circuitries are also different. Other embodiments are also described.

Description

[0001] Cross References to Related Applications [0002] This application claims priority under 35 U.S.C. 119(e) to U.S. Provisional Application No. 61 / 545,993, filed October 11, 2011, which is specifically incorporated herein by reference in its entirety. technical field [0003] Embodiments of the present invention generally relate to a system, method, and apparatus that implement a multi-row simultaneous readout scheme for a high-speed CMOS image sensor with backside illumination. Another embodiment of the present invention generally relates to a system, method and apparatus that implements a high dynamic range sub-sampling architecture. Yet another embodiment of the present invention generally relates to a system, method and apparatus implementing an arithmetic counter circuit for a high performance CMOS image sensor. Background technique [0004] High-speed image sensors have been widely used in many applications in different fields, including the automotive field, th...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H04N5/355H04N5/3745H04N5/378
CPCH04N25/531H04N25/46H04N25/57H04N25/77H04N25/78H04N25/616H04N25/704H04N25/75
Inventor 莫要武徐辰瞿旻骆晓东吴东晖
Owner OMNIVISION TECH INC
Features
  • R&D
  • Intellectual Property
  • Life Sciences
  • Materials
  • Tech Scout
Why Patsnap Eureka
  • Unparalleled Data Quality
  • Higher Quality Content
  • 60% Fewer Hallucinations
Social media
Patsnap Eureka Blog
Learn More

Browse by: Latest US Patents, China's latest patents, Technical Efficacy Thesaurus, Application Domain, Technology Topic, Popular Technical Reports.

© 2025 PatSnap. All rights reserved.Legal|Privacy policy|Modern Slavery Act Transparency Statement|Sitemap|About US| Contact US: help@patsnap.com